Plasma enhanced atomic layer deposition of SiN:H using N2 and silane

ECS Transactions

Volumn 33, Issue 2, 2010, Pages 365-373

  King, Sean W ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAYER DEPOSITION; ATOMS; ELECTRONICS INDUSTRY; NANOELECTRONICS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SILANES; SILICON; SILICON NITRIDE; TEMPERATURE; THICKNESS CONTROL; TOPOGRAPHY;

DIELECTRIC COATINGS; HYBRID TECHNIQUES; INTERCONNECT TECHNOLOGY; LOW TEMPERATURE PROCESSING; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITIONS (PE CVD); PLASMA EXPOSURE; PLASMA-ENHANCED ATOMIC LAYER DEPOSITION; STEP COVERAGE;

PLASMA CVD;

EID: 79952541954     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3485272     Document Type: Conference Paper

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