Highly-scalable disruptive reading and restoring scheme for Gb-scale SPRAM and beyond

Solid-State Electronics

Volumn 58, Issue 1, 2011, Pages 28-33

  Takemura, R ^a   Kawahara, T ^a   Ono, K ^a   Miura, K ^a,b   Matsuoka, H ^a   Ohno, H ^b  

^a HITACHI LTD   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

DDR compatible operation; Disruptive reading; Nonvolatile RAM; Spin transfer torque; SPRAM; TMR

Indexed keywords

DDR COMPATIBLE OPERATION; DISRUPTIVE READING; NONVOLATILE RAM; SPIN-TRANSFER-TORQUE; SPRAM; TMR;

DYNAMIC RANDOM ACCESS STORAGE; RESTORATION;

TORQUE;

EID: 79952282215     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2010.11.032     Document Type: Conference Paper

References (14)

1. 2 twin cell for sub 1-V operation, the institute of electronics, in-formation and communication engineers Trans Electron E90-C 4 2007 758 764 (Pubitemid 46600111)
2. M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, and K. Yamane A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM Int Electron Dev Meet (IEDM) 2005 459 462 (Pubitemid 46370888)
3. T. Kawahara, R. Takemura, K. Miura, J. Hayakawa, S. Ikeda, and Y. Lee 2 Mb SPRAM (SPin-Transfer Torque RAM) with bit-by-bit bi-directional current write and parallelizing-direction current read IEEE J Solid-State Circuits 43 1 2008 109 120
4. T. Kishi, H. Yoda, T. Kai, T. Nagase, E. Kitagawa, and M. Yoshikawa Lower-current and fast switching of a perpendicular TMR for high speed and high density spin-transfer-torque MRAM Int Electron Dev Meet (IEDM) 2008 309 312
5. K. Ono, T. Kawahara, R. Takemura, K. Miura, H. Yamamoto, and M. Yamanouchi A disturbance-free read scheme and a compact stochastic-spin- dynamics-based MTJ circuit model for Gb-scale SPRAM IEEE Int Electron Dev Meet (IEDM) 2009 9.3.1 9.3.4
6. R.H. Koch, J.A. Katine, and J.Z. Sun Time-resolved reversal of spin-transfer switching in a nanomag-net Phys Rev Lett 92 2004 088302
7. Takemura R, Kawahara T, Hayakawa J, Miura K, Ito K, Yamanouchi M, et al. TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations. In: Non-volatile semiconductor memory workshop 2008, and 2008 int conf memory technol des, NVSMW/ICMTD; 2008. p. 54-5.
8. Miura K, Kawahara T, Takemura R, Hayakawa J, Ikeda S, Sasaki R, et al. A novel SPRAM (Spintransfer torque RAM) with synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write current dispersion. In: Symp VLSI technol; 2007. p. 234-5.
9. R. Takemura, T. Kawahara, K. Miura, H. Yamamoto, J. Hayakawa, and N. Matsuzaki Localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme IEEE J Solid-State Circuits 45 4 2010 869 879
10. 2 DRAM with manufacturability and enhanced cell efficiency IEEE J Solid-State Circuits 45 4 2010 880 888
11. Endoh T, Hanyu T. Impact of spintronic devices for future nano silicon base LSI. In: Fifth international school and conference on spintronics and quantum information technology (SPINTECH V), Cracow, Poland; July, 2009.
12. J. Hayakawa, S. Ikeda, Y.M. Lee, R. Sasaki, T. Meguro, and F. Matsukura Current-driven magnetization switching in CoFeB/MgO/CoFeB magnetic tunnel junctions Jpn J Appl Phys 44 2005 1267 1270
13. C. Yoshida, M. Kurasawa, Y. Min Lee, K. Tsunoda, M. Aoki, and Y. Sugiyama A study of dielectric break-down mechanism in CoFeB/MgO/CoFeB magnetic tunnel junction IEEE Int Reliab Phys Symp 2009 139 142
14. K. Hosotani, Y. Asao, M. Nagamine, T. Ueda, H. Aikawa, and N. Shimomura Effect of interface buffer layer on the reliability of ultra-thin MgO magnetic tunnel junctions for spin transfer switching MRAM IEEE Int Reliab Phys Symp 2007 650 651 (Pubitemid 47432043)