A 31 ns random cycle VCAT-based 4F2 DRAM with manufacturability and enhanced cell efficiency

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 4, 2010, Pages 880-888

  Song, Ki Whan ^a   Kim, Jin Young ^a   Yoon, Jae Man ^a   Kim, Sua ^a   Kim, Huijung ^a   Chung, Hyun Woo ^a   Kim, Hyungi ^a   Kim, Kanguk ^a   Park, Hwan Wook ^a   Kang, Hyun Chul ^a   Tak, Nam Kyun ^a   Park, Dukha ^a   Kim, Woo Seop ^a   Lee, Yeong Taek ^a   Oh, Yong Chul ^a   Jin, Gyo Young ^a   Yoo, Jeihwan ^a   Park, Donggun ^a   Oh, Kyungseok ^a   Kim, Changhyun ^a   Jun, Young Hyun ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

4F2; Cell efficiency; Core architecture; DRAM; Hybrid sense amplifier (SA); Stack capacitor; Surrounding gate vertical channel access transistor (VCAT)

Indexed keywords

4F2; CELL EFFICIENCY; SENSE AMPLIFIER; STACK CAPACITOR; STACK CAPACITORS; SURROUNDING-GATE; VERTICAL CHANNELS;

CAPACITANCE; CAPACITORS; MIXED CONVECTION; SIMULATED ANNEALING; TRANSISTORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 77950284415     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2040229     Document Type: Conference Paper

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