Crystals and snowflakes: Building computation from nanowire crossbars

Computer

Volumn 44, Issue 2, 2011, Pages 37-45

  Dehon, André ^a   Gojman, Benjamin ^b  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

^b UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

Bottom up synthesis; Lithography; Nanowires; Programmable logic arrays (PLAs); Reconfigurable computing; Self assembly

Indexed keywords

EID: 79951861423     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2011.44     Document Type: Article

References (14)

1. Y. Cui et al., "Diameter-Controlled Synthesis of Single Crystal Silicon Nanowires," Applied Physics Letters, vol. 78, no. 15, 2001, pp. 2214-2216. (Pubitemid 33600539)
2. D. Whang et al., "Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems," Nanoletters, Sept. 2003, pp. 1255-1259. (Pubitemid 37206073)
3. C. Yang, Z. Zhong, and C.M. Lieber, "Encoding Electronic Properties by Synthesis of Axial Modulation-Doped Silicon Nanowires," Science, 25 Nov. 2005, pp. 1304-1307. (Pubitemid 41698857)
4. A. DeHon, "Nanowire-Based Programmable Architectures," ACM J. Emerging Technologies in Computing Systems, vol. 1, no. 2, 2005, pp. 109-162.
5. B. Gojman et al., "Inversion Schemes for Sublithographic Programmable Logic Arrays," IET Computers and Digital Techniques, Nov. 2009, pp. 625-642.
6. W.B. Culbertson et al., "Defect Tolerance on the TERAMAC Custom Computer," Proc. IEEE Symp. FPGAs for Custom Computing Machines (FCCM 97), IEEE Press, 1997, pp. 116-123.
7. A. DeHon and H. Naeimi, "Seven Strategies for Tolerat- ing Highly Defective Fabrication," IEEE Design and Test of Computers, July/Aug. 2005, pp. 306-315. (Pubitemid 41249776)
8. B. Gojman and A. DeHon, "VMATCH: Using Logical Varia- tion to Counteract Physical Variation in Bottom-Up, Nanoscale Systems," Proc. Int'l Conf. Field-Programmable Technology (FPT 09), IEEE Press, 2009, pp. 78-87.
9. B. Gojman et al., "3D Nanowire-Based Programmable Logic," Proc. Int'l Conf. Nano-Networks (NanoNet 06), IEEE Press, 2006, pp. 1-5.
10. Y. Luo et al., "Two-Dimensional Molecular Electronics Cir- cuits," ChemPhysChem, vol. 3, no. 6, 2002, pp. 519-525.
11. S.C. Goldstein and M. Budiu, "NanoFabrics: Spatial Com- puting Using Molecular Electronics," Proc. Int'l Symp. Computer Architectures (ISCA 01), IEEE CS Press, 2001, pp. 178-189. (Pubitemid 32826971)
12. D.B. Strukov and K.K. Likharev, "CMOL FPGA: A Recon- figurable Architecture for Hybrid Digital Circuits with Two-Terminal Nanodevices," Nanotechnology, June 2005, pp. 888-900. (Pubitemid 40666599)
13. G.S. Snider and R.S. Williams, "Nano/CMOS Archi- tectures Using a Field-Programmable Nanowire Interconnect," Nanotechnology, Jan. 2007; http://iopscience. iop.org/0957-4484/18/3/035204.
14. J.E. Green et al., "A 160-Kilobit Molecular Electronic Memory Patterned at 1011 Bits Per Square Centimetre," Nature, 25 Jan. 2007, pp. 414-417. (Pubitemid 46160906)