Modeling out-of-order processors for WCET analysis

Real-Time Systems

Volumn 34, Issue 3, 2006, Pages 195-227

  Li, Xianfeng ^a   Roychoudhury, Abhik ^b   Mitra, Tulika ^b  

^a PEKING UNIVERSITY   (China)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Branch prediction; Instruction cache; Out of order superscalar processor; Worst case execution time (WCET) analysis

Indexed keywords

BRANCH PREDICTION; INSTRUCTION CACHE; OUT-OF-ORDER SUPERSCALAR PROCESSOR; WORST-CASE EXECUTION TIME (WCET) ANALYSIS;

BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; INTEGER PROGRAMMING; LINEAR PROGRAMMING; MATHEMATICAL MODELS; PIPELINES; REAL TIME SYSTEMS; SCHEDULING; TIME MEASUREMENT;

PROGRAM PROCESSORS;

EID: 33747319225     PISSN: 09226443     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11241-006-9205-5     Document Type: Article

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