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Volumn , Issue , 2009, Pages 119-128

Preciseworst-case execution time analysis for processors with timing anomalies

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL-FLOW GRAPHS; DECOMPOSITION TECHNIQUE; DIVIDE AND CONQUER; EXECUTION TIME; HARDWARE COMPONENTS; HARDWARE DESIGNERS; STATE OF THE ART; STATE SPACE; SUBGRAPHS;

EID: 70449589505     PISSN: 10683070     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECRTS.2009.8     Document Type: Conference Paper
Times cited : (22)

References (19)
  • 6
    • 0029546911 scopus 로고
    • Efficient microarchitecture modeling and path analysis for real-time software
    • Dec.
    • Y.-T. S. Li, S. Malik, and A. Wolfe, "Efficient microarchitecture modeling and path analysis for real-time software," in Proc. IEEE Real-Time Systems Symposium, Dec. 1995, pp. 298-307.
    • (1995) Proc. IEEE Real-Time Systems Symposium , pp. 298-307
    • Li, Y.-T.S.1    Malik, S.2    Wolfe, A.3
  • 7
    • 0031186994 scopus 로고    scopus 로고
    • Computing maximum task execution times - A graph-based approach
    • P. Puschner and A. V. Schedl, "Computing maximum task execution times - a graph-based approach," Journal of RealTime Systems, vol.13, pp. 67-91, 1997.
    • (1997) Journal of RealTime Systems , vol.13 , pp. 67-91
    • Puschner, P.1    Schedl, A.V.2
  • 8
    • 0033732401 scopus 로고    scopus 로고
    • Timing analysis for instruction caches
    • May
    • F.Mueller, "Timing analysis for instruction caches," Journal of Real-Time Systems, vol. 18, no. 2/3, pp. 209-239, May 2000.
    • (2000) Journal of Real-Time Systems , vol.18 , Issue.2-3 , pp. 209-239
    • Mueller, F.1
  • 10
    • 0014477093 scopus 로고
    • Bounds on multiprocessing timing nomalies
    • R. L. Graham, "Bounds on multiprocessing timing nomalies," SIAM Journal of Applied Mathematics, vol.17, no.2, pp. 416-429, 1969.
    • (1969) SIAM Journal of Applied Mathematics , vol.17 , Issue.2 , pp. 416-429
    • Graham, R.L.1
  • 19
    • 70449619621 scopus 로고    scopus 로고
    • Neutralizing timing anomalies in complex computer architectures
    • Vienna, Austria, Nov.
    • A. Kadlec and R. Kirner, "Neutralizing timing anomalies in complex computer architectures," in Proc. Junior Scientist Conference, Vienna, Austria, Nov. 2008, pp. 119-120.
    • (2008) Proc. Junior Scientist Conference , pp. 119-120
    • Kadlec, A.1    Kirner, R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.