-
1
-
-
33744495995
-
Classification of WCET analysis techniques
-
Seattle, WA, May
-
R. Kirner and P. Puschner, "Classification of WCET analysis techniques," in Proc. 8th IEEE International Symposium on Object-oriented Real-time distributed Computing, Seattle, WA, May 2005, pp. 190-199.
-
(2005)
Proc. 8th IEEE International Symposium on Object-oriented Real-time Distributed Computing
, pp. 190-199
-
-
Kirner, R.1
Puschner, P.2
-
2
-
-
43949126892
-
The worst-case execution time problem - Overview of methods and survey of tools
-
Apr.
-
R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckman, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenstrom, "The worst-case execution time problem - overview of methods and survey of tools," ACM Transactions on Embedded Computing Systems (TECS), vol.7, no.3, Apr. 2008.
-
(2008)
ACM Transactions on Embedded Computing Systems (TECS)
, vol.7
, Issue.3
-
-
Wilhelm, R.1
Engblom, J.2
Ermedahl, A.3
Holsti, N.4
Thesing, S.5
Whalley, D.6
Bernat, G.7
Ferdinand, C.8
Heckman, R.9
Mitra, T.10
Mueller, F.11
Puaut, I.12
Puschner, P.13
Staschulat, J.14
Stenstrom, P.15
-
4
-
-
33947355055
-
Principles of timing anomalies in superscalar processors
-
Melbourne, Australia, Sep.
-
I. Wenzel, R. Kirner, P. Puschner, and B. Rieder, "Principles of timing anomalies in superscalar processors," in Proc. 5th International Conference of Quality Software, Melbourne, Australia, Sep. 2005.
-
(2005)
Proc. 5th International Conference of Quality Software
-
-
Wenzel, I.1
Kirner, R.2
Puschner, P.3
Rieder, B.4
-
5
-
-
38849129464
-
A definition and classification of timing anomalies
-
Dresden, Germany, July
-
J. Reineke, B. Wachter, S. Tesing, R. Wilhelm, I. Polian, J. Eisinger, and B. Becker, "A definition and classification of timing anomalies," in Proc. 6th International Workshop on Worst-Case Execution Time Analysis, Dresden, Germany, July 2006.
-
(2006)
Proc. 6th International Workshop on Worst-Case Execution Time Analysis
-
-
Reineke, J.1
Wachter, B.2
Tesing, S.3
Wilhelm, R.4
Polian, I.5
Eisinger, J.6
Becker, B.7
-
6
-
-
0029546911
-
Efficient microarchitecture modeling and path analysis for real-time software
-
Dec.
-
Y.-T. S. Li, S. Malik, and A. Wolfe, "Efficient microarchitecture modeling and path analysis for real-time software," in Proc. IEEE Real-Time Systems Symposium, Dec. 1995, pp. 298-307.
-
(1995)
Proc. IEEE Real-Time Systems Symposium
, pp. 298-307
-
-
Li, Y.-T.S.1
Malik, S.2
Wolfe, A.3
-
7
-
-
0031186994
-
Computing maximum task execution times - A graph-based approach
-
P. Puschner and A. V. Schedl, "Computing maximum task execution times - a graph-based approach," Journal of RealTime Systems, vol.13, pp. 67-91, 1997.
-
(1997)
Journal of RealTime Systems
, vol.13
, pp. 67-91
-
-
Puschner, P.1
Schedl, A.V.2
-
8
-
-
0033732401
-
Timing analysis for instruction caches
-
May
-
F.Mueller, "Timing analysis for instruction caches," Journal of Real-Time Systems, vol. 18, no. 2/3, pp. 209-239, May 2000.
-
(2000)
Journal of Real-Time Systems
, vol.18
, Issue.2-3
, pp. 209-239
-
-
Mueller, F.1
-
9
-
-
84947261898
-
Reliable and precise WCET determination for a reallife processor
-
Tahoe City, CA, USA, Oct.
-
C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, and R. Wilhelm, "Reliable and precise WCET determination for a reallife processor," in Proc. of the 1st International Workshop on Embedded Software (EMSOFT 2001), Tahoe City, CA, USA, Oct. 2001, pp. 469-485.
-
(2001)
Proc. of the 1st International Workshop on Embedded Software (EMSOFT 2001)
, pp. 469-485
-
-
Ferdinand, C.1
Heckmann, R.2
Langenbach, M.3
Martin, F.4
Schmidt, M.5
Theiling, H.6
Thesing, S.7
Wilhelm, R.8
-
10
-
-
0014477093
-
Bounds on multiprocessing timing nomalies
-
R. L. Graham, "Bounds on multiprocessing timing nomalies," SIAM Journal of Applied Mathematics, vol.17, no.2, pp. 416-429, 1969.
-
(1969)
SIAM Journal of Applied Mathematics
, vol.17
, Issue.2
, pp. 416-429
-
-
Graham, R.L.1
-
11
-
-
22444435996
-
-
PhD Thesis, Universität des Saarlandes, Saarbrücken, Germany, Dec.
-
J. Schneider, "Combined schedulability and wcet analysis for real-time operating systems," PhD Thesis, Universität des Saarlandes, Saarbrücken, Germany, Dec. 2002.
-
(2002)
Combined Schedulability and Wcet Analysis for Real-time Operating Systems
-
-
Schneider, J.1
-
13
-
-
33947405209
-
-
Master's thesis, Technische Universität Wien, Vienna, Austria
-
I. Wenzel, "Principles of timing anomalies in superscalar processors," Master's thesis, Technische Universität Wien, Vienna, Austria, 2003.
-
(2003)
Principles of Timing Anomalies in Superscalar Processors
-
-
Wenzel, I.1
-
15
-
-
33847136076
-
Automatic identification of timing anomalies for cycle-accurate worst-case execution time analysis
-
IEEE Computer Society
-
J. Eisinger, I. Polian, B. Becker, A. Metzner, S. Thesing, and R. Wilhelm, "Automatic identification of timing anomalies for cycle-accurate worst-case execution time analysis," in Proc, 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. IEEE Computer Society, 2006, pp. 15-20.
-
(2006)
Proc, 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
, pp. 15-20
-
-
Eisinger, J.1
Polian, I.2
Becker, B.3
Metzner, A.4
Thesing, S.5
Wilhelm, R.6
-
16
-
-
49649115872
-
Obstacles in worst-cases execution time analysis
-
Orlando, Florida, May
-
R. Kirner and P. Puschner, "Obstacles in worst-cases execution time analysis," in Proc. 11th IEEE International Symposium on Object-oriented Real-time distributed Computing, Orlando, Florida, May 2008, pp. 333-339.
-
(2008)
Proc. 11th IEEE International Symposium on Object-oriented Real-time Distributed Computing
, pp. 333-339
-
-
Kirner, R.1
Puschner, P.2
-
17
-
-
70449582902
-
-
Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 1-3/182-1, 1040 Vienna, Austria, Research Report 01/2009
-
R. Kirner, A. Kadlec, and P. Puschner, "Worst-case execution time analysis for processors showing timing anomalies," Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 1-3/182-1, 1040 Vienna, Austria, Research Report 01/2009, 2009.
-
(2009)
Worst-case Execution Time Analysis for Processors Showing Timing Anomalies
-
-
Kirner, R.1
Kadlec, A.2
Puschner, P.3
-
19
-
-
70449619621
-
Neutralizing timing anomalies in complex computer architectures
-
Vienna, Austria, Nov.
-
A. Kadlec and R. Kirner, "Neutralizing timing anomalies in complex computer architectures," in Proc. Junior Scientist Conference, Vienna, Austria, Nov. 2008, pp. 119-120.
-
(2008)
Proc. Junior Scientist Conference
, pp. 119-120
-
-
Kadlec, A.1
Kirner, R.2
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