Hierarchical analog/mixed-signal circuit optimization under process variations and tuning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 2, 2011, Pages 313-317

  Yu, Guo ^a,b   Li, Peng ^a  

^a Department of Electrical and Computer Engineering   (United States)

^b Microelectronics Division of Oracle America   (United States)

Author keywords

Analog; mixed signal; optimization; postsilicon tuning; yield

Indexed keywords

ANALOG; ANALOG/MIXED-SIGNAL CIRCUITS; BUILDING BLOCKES; CIRCUIT BLOCKS; HIERARCHICAL OPTIMIZATION; MANUFACTURABILITY; MIXED SIGNAL; MIXED-SIGNAL SYSTEMS; MULTIPLE BUILDINGS; OPTIMIZATION FRAMEWORK; OPTIMIZATION PROBLEMS; PARETO MODEL; PERFORMANCE CHARACTERIZATION; PHASED-LOCKED LOOPS; POST-SILICON; PROCESS VARIATION; SCALED TECHNOLOGIES; SELFTUNING; SYSTEM LEVELS; SYSTEM OPTIMIZATIONS; YIELD;

ANALOG CIRCUITS; ELECTRIC SIGNAL SYSTEMS; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT MANUFACTURE; STRUCTURAL DESIGN; SYSTEMS ANALYSIS; TUNING;

OPTIMIZATION;

EID: 78951481857     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2071250     Document Type: Conference Paper

References (14)

1. J. Zou, D. Mueller, H. Graeb, and U. Schlichtmann, "A CPPLL hierarchical optimization methodology considering jitter, power and locking time," in Proc. IEEE/ACM DAC, 2006, pp. 19-24.
2. A. Nieuwoudt, T. Ragheb, and Y. Massoud, "SOC-NLNA: Synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers," in Proc. IEEE/ACM DAC, 2006, pp. 879-884.
3. T. Eeckelaert, R. Schoofs, G. Gielen, M. Steyaert, and W. Sansen, "Hierarchical bottom-up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11 a/b/g standard," in Proc. IEEE/ACM DAC, 2006, pp. 25-30.
4. G. Gielen, T. McConaghy, and T. Eeckelaer, "Performance space modeling for hierarchical synthesis of analog integrated circuits," in Proc. IEEE/ACM DAC, 2005, pp. 881-886.
5. T. McConaghy, P. Palmers, G. Gielen, and M. Steyaert, "Simultaneous topology multiobjective sizing across thousands of analog circuit topologies," in Proc. IEEE/ACM DAC, 2007, pp. 944-947.
6. B. Smedt and G. Gielen, "HOLMES: Capturing the yield-optimized design space boundaries of analog and RF integrated circuits," in Proc. IEEE/ACM DATE, 2003, pp. 19-24.
7. X. Li, P. Gopalakrishna, Y. Xu, and L. Pileggi, "Robust analog/rf circuit design with projection-based polynomial modeling," in Proc. IEEE/ACM ICCAD, 2004, pp. 855-862.
8. S. Tiwary, P. Tiwary, and R. Rutenbar, "Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration," in Proc. IEEE/ACM DAC, 2006, pp. 31-36.
9. C. Liang, S. Chen, and S. Liu, "A digital calibration technique for charge pumps in phase-locked systems," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 390-398, Feb. 2008.
10. H. G. D. Mueller-Gritschneder and U. Schlichtmann, "A successive approach to compute the bounded Pareto front of practical multiobjective optimization problems," SIAM J. Optim., vol. 20, no. 2, pp. 915-934, 2009.
11. H. Graeb, D. Mueller-Gritschneder, and U. Schlichtmann, "Pareto optimization of analog circuits considering variability," Int. J. Circuit Theory Appl., vol. 37, no. 2, pp. 283-299, 2009.
12. G. Yu and P. Li, "Yield-aware analog integrated circuit optimization using geostatistics motivated parametric failures," in Proc. IEEE/ACM ICCAD, 2007, pp. 464-469.
13. W. Huyer and A. Neumaier, "Global optimization by multilevel coordinate search," J. Global Optim., vol. 14, no. 4, pp. 331-355, Jun. 1999.
14. M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-States Circuits, vol. 24, no. 5, pp. 1433- 1440, Oct. 1989.