A CPPLL hierarchical optimization methodology considering jitter, power and locking time

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 19-24

  Zou, Jun ^a   Mueller, Daniel ^a   Graeb, Helmut ^a   Schlichtmann, Ulf ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

Hierarchical optimization; Pareto optimal fronts

Indexed keywords

ANALOG CIRCUITS; COMPUTER SIMULATION; JITTER; PARETO PRINCIPLE; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

BEHAVIORAL MODELING; LOCKING TIME; MULTIDIMENSIONAL PARETO-OPTIMAL FRONTS; NONLINEAR LOCKING;

HIERARCHICAL SYSTEMS;

EID: 34547172863     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146919     Document Type: Conference Paper

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