Hierarchical bottom-up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 25-30

  Eeckelaert, Tom ^a   Schoofs, Raf ^a   Gielen, Georges ^a   Steyaert, Michiel ^a   Sansen, Willy ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Hierarchical synthesis

Indexed keywords

ANALOG TO DIGITAL CONVERSION; OPTIMIZATION; SOFTWARE DESIGN; SPECIFICATIONS; WIRELESS LOCAL AREA NETWORKS (WLAN);

ANALOG BLOCKS; DELTA-SIGMA; MULTI - OBJECTIVE EVOLUTIONARY; TRADEOFF OFFERS;

HIERARCHICAL SYSTEMS;

EID: 33847644784     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146920     Document Type: Conference Paper

References (15)

1. H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E. Liu, A. Malvasi, A. L. Sangiovanni-Vincentelli, and I. Vassiliou. A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits. Kluwer Academic Publishers, 1997.
2. A. Doboli, N. Dhanwada, A. Nunez-Aldana, and R. Vemuri. A Two-Layer Library-Based Approach to Synthesis of Analog Systems from VHDL-AMS Specifications. ACM Transactions on Design Automation of Electronic System, 9(2):238-271, Apr. 2004.
3. S. Donnay, G. G. E. Gielen, W. Saneen, W. Kruiskamp, D. Leenaerts, S. Buytaert, K. Marent, M. Buckens, and C. Das. Using Top-Down CAD Tools for Mixed Analog/Digital ASIC's: a Practical Design Case. Journal of Analog Integrated Circuits and Signal Processing, 10:101-117, 1996.
4. T. Eeckelaert, T. McConaghy, and G. G. E. Gielen. Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-optimal Performance Hypersurfaces. In Proceedings Design Automation and Test in Europe Conference, pages 1070-1075, 2005.
5. G. G. E. Gielen, T. McConaghy, and T. Eeckelaert. Performance Space Modeling for Hierarchical Synthesis of Analog Integrated Circuits. In Proceedings Design Automation Conference, pages 881-886, June 2005.
6. G. G. E. Gielen and R. A. Rutenbar. Computer-aided design of analog and mixed-signal integrated circuits. Proceedings of the IEEE, 88(12):1825-1852, Dec. 2000.
7. R. Harjani and J. Shao. Feasibility and Performance Region Modeling of Analog an Digital Circuits. Journal of Analog Integrated Circuits and Signal Processing, 10(1):23-43, June 1996.
8. J. Kleinberg. Two algorithms for nearest-neighbor search in high dimensions. In Proc. the ACM Symposium on Theory of Computing, Feb. 1997.
9. R. Phelps, M. Krasnicki, R. A. Rutenbar, L. R. Carley, and J. R. Heliums. A Case Study of Synthesis for Industrial-Scale Analog IP: Redesign of the Equalizer/Filter Frontend for an ADSL CODEC. In Proc. Design Automation Conference, pages 1-6, 2000.
10. R, Schoofs, M. Steyaert, and W. Sansen. A GmC filter design methodology for high-speed continuous-time A/D converters in a deep sub-micron technology. In VLSI Circuits and Systems II Conf., Sevilla, May 2005.
11. R. Schoofs, M. Steyaert, and W. Sansen. Current-Steering DAC Design for High-Speed Continuous-Time Sigma-Delta A/D Converters. In DCIS'05, Lisbon, Nov. 2005.
12. G. Stehr, H. Graeb, and K. Antreich. Feasibility Regions and their Significance to the Hierarchical Optimization of Analog and Mixed-Signal Systems. International Series of Numerical Mathematics, 146:167-184, 2003.
13. G. Van der Plas, G. Debyser, F. Leyn, K. Lampaert, J. Vandenbussche, G. G. E. Gielen, W. Sansen, P. Veselinovic, and D. Leenaerts. AMGIE -A Synthesis Environment for CMOS Analog Integrated Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(9):1037-1058, Sept. 2001.
14. E. Zitzler. Evolutionary Algorithms for Multiobjective Optimization: Methods and Applications. PhD thesis, Swiss Federal Institute of Technology, Zurich, Switzerland, 1999.
15. E. Zitzler and L. Thiele. Multiobjective Evolutionary Algorithms: A Comparative Case Study and the Strength Pareto Approach. Transactions on Evolutionary Computation, 3(4):257-271, Nov. 1999.