Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 31-36

  Tiwary, Saurabh K ^a   Tiwary, Pragati K ^b   Rutenbar, Rob A ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b BIRLA INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Optimization; Pareto surfaces; Performance space; Yield

Indexed keywords

ALGORITHMS; GLOBAL OPTIMIZATION; HIERARCHICAL SYSTEMS; MONTE CARLO METHODS; PHASE LOCKED LOOPS; PHASE NOISE; VARIABLE FREQUENCY OSCILLATORS;

PARETO SURFACES; PERFORMANCE SPACE; SINGLE CIRCUIT SYNTHESIS;

PARETO PRINCIPLE;

EID: 34547327558     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146921     Document Type: Conference Paper

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