Ultra thin hermetic wafer level, chip scale package

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 1122-1128

  Shiv, L ^a   Heschel, M ^a   Korth, H ^b   Weichel, S ^a   Hauffe, R ^b   Kilian, A ^b   Semak, B ^a   Houlberg, M ^a   Egginton, P ^a   Hase, A ^b   Kuhmann, J ^b  

^a Hymite A/S   (Denmark)

^b Hymite GmbH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC PROPERTIES; MICROELECTROMECHANICAL DEVICES; OPTICAL INTERCONNECTS; SOLDERING; SURFACE MOUNT TECHNOLOGY;

HANDHELD DEVICES; SURFACE MOUNTABLE (SMT) PACKAGES; THROUGH WAFER INTERCONNECTS; WAFER LEVEL CHIP SIZE PACKAGING (WLCSP);

CHIP SCALE PACKAGES;

EID: 33845561908     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645794     Document Type: Conference Paper

References (6)

1. Yun et al, "Wafer-Level Packaging of MEMS Accelerometers with Through-Wafer Interconnects", 2005 Electronic Components and Technology Conference, IEEE, pp. 320-323 (2005).
2. Woonbae et al, "A Low Temperature, Hermetic Wafer Level Packaging Methd for RF MEMS Switch", 2005 Electronic Components and Technology Conference, IEEE, pp. 1103-1108 (2005).
3. Felton et al., "Chip Scale Packaging of a MEMS Accelerometer", 2004 Electronic Components and Technology Conference, IEEE, pp. 869-873 (2004).
4. Leib et al., "New Wafer-Level-Packaging Technology using Silicon-Via-Contacts For Optical And Other Sensor Applications", 2004 Electronic Components and Technology Conference, IEEE, pp. 843-847 (2004).
5. Elger et al.: "Optical Leak Detection for Wafer Level Hermeticily Testing", SEMICON West 2004, 14-16 July 2004, San Jose, CA.
6. Hauffe et al.: "Optimized Micro-Via Technology for High Density and High Frequency (>40GHz) Hermetic Through-Wafer Connections in Silicon Substrates", 2005 Electronic Components and Technology Conference, IEEE, pp. 324-330 (2005).