Process integration of fine pitch micro-bumping and Cu redistribution wiring for power efficient SiP

Electronics System Integration Technology Conference, ESTC 2010 - Proceedings

Volumn , Issue , 2010, Pages

  Ezawa, Hirokazu ^a   Togasaki, Takashi ^a   Migita, Tatsuo ^a   Yamashita, Soichi ^a   Inohara, Masahiro ^a   Koshio, Yasuhiro ^a   Fukuda, Masatoshi ^a   Miyata, Masahiro ^a   Nagamine, Koro ^a   Iijima, Tadashi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

300 MM WAFERS; CHIP STACKING; CHIP-ON-CHIP; DRAM CHIPS; EMBEDDED DRAM; FINE PITCH; LEADING EDGE; LOGIC CHIPS; LOGIC TECHNOLOGY; LOWER-POWER CONSUMPTION; MEMORY BANDWIDTHS; POWER EFFICIENT; PROCESS INTEGRATION; SOC (SYSTEM ON CHIP); SYSTEM IN PACKAGE;

DYNAMIC RANDOM ACCESS STORAGE; FLIGHT DYNAMICS; INTERNET PROTOCOLS; MICROPROCESSOR CHIPS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 78651283047     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2010.5642887     Document Type: Conference Paper

References (7)

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