Low-stress interconnection for flip chip BGA employing lead-free solder bump

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 885-891

  Uchida, Masayuki ^a   Ito, Hisashi ^a   Yabui, Ken ^a   Nishiuchi, Hideo ^a   Togasaki, Takashi ^a   Higuchi, Kazuhito ^a   Ezawa, Hirokazu ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FLIP CHIP BONDING TECHNOLOGY; HIGH-END LOGIC LSI; LEAD-FREE SOLDER BUMP; LOW-STRESS INTERCONNECTION;

ANNEALING; CREEP; ENVIRONMENTAL IMPACT; ERRORS; INTERCONNECTION NETWORKS; LSI CIRCUITS;

FLIP CHIP DEVICES;

EID: 35348915925     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373903     Document Type: Conference Paper

References (7)

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2. K. Higuchi, M. Seto, M. Uchida, T. Togasaki, H. Ezawa, "Development of Sn-Cu Bumping by Alloying Cu/Sn Metal Stacks," Proc. International Symposium on Microelectronics, pp. 1035-1042, 2006.
3. A. Miyamoto, T. Ogawa, T. Ohsawa, "Prediction of Mechanical Properties of Lead-Free Solders", J. Soc. Mat. Sci., Jpn., Vol. 51, No. 4, pp. 445-450, Apr. 2002. [in Japanese]
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7. T. Nishiyama, H. Kohketsu, K. Tkahashi, T. Ogawa, T. Ohsawa, "Influence of Microstructure on Creep Properties of solders", Journal of Japan Institute of Electronics Packaging, vol. 9, No. 3, pp. 162-170, 2006. [in Japanese]