A 222mW H.264 full-HD decoding application processor with x512b stacked DRAM in 40nm

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 326-327

  Kikuchi, Yu ^a   Takahashi, Makoto ^a   Maeda, Tomohisa ^a   Hara, Hiroyuki ^a   Arakida, Hideho ^a   Yamamoto, Hideaki ^a   Hagiwara, Yousuke ^a   Fujita, Tetsuya ^a   Watanabe, Manabu ^a   Shimazawa, Takayoshi ^a   Ohara, Yasuo ^a   Miyamori, Takashi ^a   Hamada, Mototsugu ^a   Takahashi, Masafumi ^a   Oowaki, Yukihito ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

3D GRAPHICS; APPLICATION PROCESSORS; CHIP-ON-CHIP; DRAM CHIPS; HARDWARE ENGINES; HARDWARE SOLUTIONS; HIGH DEFINITION; HIGH MEMORY BANDWIDTH; HIGH POWER CONSUMPTION; HYBRID ARCHITECTURES; LOGIC CHIPS; LOW POWER; LOW-POWER CONSUMPTION; METAL LAYER; MICRO-BUMPS; MULTI-CORE PROCESSOR; MULTIMEDIA APPLICATIONS; MULTIPLE LOGIC; NEW APPLICATIONS; ON CHIPS; PERFORMANCE REQUIREMENTS; PERFORMANCE TASKS; POWER DOMAIN; POWER EFFICIENT; RE-DISTRIBUTION; SIMPLE STRUCTURES; SOFTWARE SOLUTION; SYSTEM-IN-PACKAGE; VIDEO PROCESSING;

COMPUTER ARCHITECTURE; DYNAMIC RANDOM ACCESS STORAGE; HARDWARE; MICROPROCESSOR CHIPS; MOBILE DEVICES; NANOTECHNOLOGY; PORTABLE EQUIPMENT; PROGRAMMABLE LOGIC CONTROLLERS;

THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 77952202978     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433906     Document Type: Conference Paper

References (6)

1. K. Iwata, et al., "A 342mW Mobile Application Processor with Full-HD Multi- Standard Video Codec," ISSCC Dig. Tech. Papers, pp. 158-159, Feb. 2009.
2. G. Gammie, et al., "A 45nm Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques," ISSCC Dig. Tech. Papers,pp. 258-259, Feb. 2008.
3. M. Shirasaki, et al., "A 45nm Single-Chip Application-and-Baseband Processor Using an Intermittent Operation Technique," ISSCC Dig. Tech. Papers, pp. 156-157, Feb. 2009.
4. S. Nomura, et al., "A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 262-263, Feb. 2008.
5. T. Ezaki, et al., "A 160Gb/s Interface Design Configuration for Multichip LSI," ISSCC Dig. Tech. Papers, pp. 140-141, Feb. 2004.
6. Y. Kanno, et al., "Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor," ISSCC Dig. Tech. Papers, pp. 540-541, Feb. 2006.