A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications

Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010

Volumn , Issue , 2010, Pages 13-18

  Valinataj, Mojtaba ^a,b   Mohammadi, Siamak ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

^b BABOL NOSHIRVANI UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

Congestion; Fault tolerance; Network on chip; Reconfiguration; Reliability; Routing algorithm

Indexed keywords

ADAPTIVE ROUTING ALGORITHM; ADAPTIVITY; ADDITIONAL COSTS; CONGESTION; FAULT-TOLERANCE CAPABILITY; FAULTY LINKS; IRREGULAR TOPOLOGY; LOW COSTS; MULTI-LEVEL; MULTIPLE COMPONENTS; NETWORK ON CHIP; NETWORKS ON CHIPS; POWER OVERHEAD; RE-CONFIGURABLE; RECONFIGURABILITY; RECONFIGURATION; RELIABILITY IMPROVEMENT; ROUTING METHODS; VIRTUAL CHANNELS;

ADAPTIVE ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; FAULT TOLERANCE; MESH NETWORKING; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; ROUTERS; ROUTING ALGORITHMS; SERVERS; VLSI CIRCUITS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 78650963659     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2010.5642628     Document Type: Conference Paper

References (13)

1. P. H. Sui and S. D. Wang, "Fault-tolerant wormhole routing algorithm for mesh networks," IEE Proc. Comput. & Digit. Tech., vol. 147, no. 1, pp. 9-14, 2000.
2. C. L. Chen and G. M. Chiu, "A fault-tolerant routing scheme for meshes with nonconvex faults," IEEE Trans. on Parallel and Distributed Syst., vol. 12, no. 5, pp. 467-475, 2001.
3. D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan and C. R. Das, "Exploring fault-tolerant Network-on-Chip architectures," Int. Conf. on Dependable Systems and Networks (DSN), pp. 93-104. 2006.
4. S.-Y. Lin, W.-C. Shen, C.-C. Hsu, C.-H. Chao and A.-Y. Wu, "Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems," Int. Symp. on VLSI Design, Automation and Test (VLSI-DAT), pp. 72-75, 2009.
5. Z. Zhang, A. Greiner and S. Taktak, "A reconfigurable routing algorithm for a fault-tolerant 2D-mesh Network-on-Chip," Design Automation Conference (DAC), pp. 441-446, 2008.
6. M. Valinataj, S. Mohammadi, S. Safari and J. Plosila, "A link failure aware routing algorithm for Networks-on-Chip in nano technologies," IEEE Conference on Nanotechnology, pp. 841-844, 2009.
7. Y. B. Kim and Y.-B. Kim, "Fault tolerant source routing for Network-on-Chip, " IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), pp. 12-20, 2007.
8. D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester and D. Blaauw, "A highly resilient routing algorithm for fault-tolerant NoCs," Design, Automation and Test in Europe Conf. (DATE), pp. 21-26, 2009.
9. T. Schonwald, J. Zimmermann, O. Bringmann and W. Rosenstiel, "Fully adaptive fault-tolerant routing algorithm for Network-on-Chip architectures," Euromicro Conf. on Digital System Design Architectures, Methods and Tools (DSD), pp. 527-534, 2007.
10. R. Ubar and J. Raik, "Testing strategies for Network on Chip, Networks on Chip," A. Jantsch and H. Tenhunen (ed.), Kluwer Academic Publisher, pp. 131-152, 2003.
11. M. Li, Q. A. Zeng and W. B. Jone, "DyXY - A proximity congestion-aware deadlock-free dynamic routing method for Network on Chip," Design Automation Conference (DAC), pp. 849-852, 2006.
12. W. Dally and C. Seitz, "Deadlock-free message routing in multiprocessor interconnection networks," IEEE Trans. on Computers, vol. 36, no. 5, pp. 547-553, 1987.
13. A. Jalabert, S. Murali, L. Benini and G. De Micheli, " xpipesCompiler: A tool for instantiating application specific Networks on Chip," Design Automation and Test in Europe Conf. (DATE), pp. 884-889, 2004.