Design hierarchy guided multilevel circuit partitioning

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2002, Pages 30-35

  Cheon, Yongseok ^a   Wong, D F ^a  

^a University of Texas at Austin   (United States)

Author keywords

Circuit partitioning; Clustering; Design hierarchy; Rent's rule

Indexed keywords

ALGORITHMS; DESIGN FOR TESTABILITY; ITERATIVE METHODS; ROUTERS;

CIRCUIT PARTITIONING;

VLSI CIRCUITS;

EID: 0036374258     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505388.505398     Document Type: Conference Paper

References (12)

1. Recent directions in netlist partitioning: A survey
2. Multilevel circuit partitioning
3. Hierarchical partitioning
4. Multi-way Fpga partitioning by fully exploiting design hierarchy
5. A linear time heuristic for improving network partitions
6. On the intrinsic Rent parameter and spectra-based partitioning methodologies
7. Multilevel hypergraph partitioning: Application in VLSI domain
8. Multilevel k-way hypergraph partitioning
9. An efficient heuristic procedure for partitioning of electrical circuits
10. A hierarchy-driven FPGA partitioning method
11. A new optimization driven clustering algorithm for large circuits
12. Improvements of a mincut partition algorithm