An integrated test chip for the complete characterization and monitoring of a 0.25um CMOS technology that fits into five scribe line structures 150um by 5,000um

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2003, Pages 59-63

  Lefferts, Robert ^a   Jakubiec, Chris ^a  

^a Accelerant Networks   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS; SIGNAL PROCESSING; SILICON; TRANSISTORS;

TEST DEVICES;

CMOS INTEGRATED CIRCUITS;

EID: 0038642569     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A. Steegen, M. Stucchi, A. Lauwers, K. Maex, "Suicide Induced pattern density and orientation dependent transonductance in MOS transistors", IEDM 1999, pp. 497-500.
2. B. R. Blaes, M. G. Buehler, Y-S Lin, K.A. Hicks, "A CMOS matrix for extracting mosfet parameters before and after irradiation", IEEE Transactions on Nuclear Science, Vol. 35, No. 6, December 1988
3. L. Portmann, C. Lallement, F. Krummenacher, "A high density integrated test matrix of MOS transistors for matching study", IEEE Conference on Microelectronic Test Structures, Vol. 11, March 1198, pp. 19-24.
4. J. Chen, et al.,"An On-Chip Attofarad Interconnect Charge-Based Capacitance Measurement Technique," 1996 Proc. of IEDM, pp. 69-72.