-
1
-
-
34547471544
-
Design tradeoffs for tiled cmp on-chip networks
-
J. Balfour and W.J. Dally. Design tradeoffs for tiled cmp on-chip networks. In ICS, 2006.
-
(2006)
ICS
-
-
Balfour, J.1
Dally, W.J.2
-
2
-
-
0025433355
-
Virtual-channel flow control
-
May
-
W. J. Dally. Virtual-channel flow control. In ISCA, May 1990.
-
(1990)
ISCA
-
-
Dally, W.J.1
-
3
-
-
0029390484
-
A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks
-
J. Duato. A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks. TPDS, 6(10):1055-1067, 1995.
-
(1995)
TPDS
, vol.6
, Issue.10
, pp. 1055-1067
-
-
Duato, J.1
-
4
-
-
8344288141
-
Adaptive channel queue routing on k-ary n-cubes
-
A. Singh et al. Adaptive channel queue routing on k-ary n-cubes. In SPAA, 2004.
-
(2004)
SPAA
-
-
Singh, A.1
-
5
-
-
27544463701
-
Near-optimal worst-case throughput routing for two-dimensional mesh networks
-
June
-
D. Seo et al. Near-optimal worst-case throughput routing for two-dimensional mesh networks. In ISCA, June 2005.
-
(2005)
ISCA
-
-
Seo, D.1
-
6
-
-
36348975404
-
Implementation and evaluation of on-chip network architectures
-
Oct.
-
P. Gratz et al. Implementation and evaluation of on-chip network architectures. In ICCD, Oct. 2006.
-
(2006)
ICCD
-
-
Gratz, P.1
-
7
-
-
57749191721
-
Regional congestion awareness for load balance in networks-on-chip
-
Feb.
-
P. Gratz et al. Regional congestion awareness for load balance in networks-on-chip. In HPCA, Feb. 2008.
-
(2008)
HPCA
-
-
Gratz, P.1
-
9
-
-
70450250424
-
Indirect adaptive routing on large scale interconnection networks
-
June
-
N. Jiang et al. Indirect adaptive routing on large scale interconnection networks. In ISCA, June. 2009.
-
(2009)
ISCA
-
-
Jiang, N.1
-
11
-
-
47349129525
-
Flattened butterfly topology for on-chip networks
-
J. Kim, J. Balfour, and W.J. Dally. Flattened butterfly topology for on-chip networks. In MICRO, 2007.
-
(2007)
MICRO
-
-
Kim, J.1
Balfour, J.2
Dally, W.J.3
-
12
-
-
27944435722
-
A low latency router supporting adaptivity for on-chip interconnects
-
J. Kim et al. A low latency router supporting adaptivity for on-chip interconnects. In DAC, 2005.
-
(2005)
DAC
-
-
Kim, J.1
-
14
-
-
35348858651
-
Express virtual channels: Towards the ideal interconnection fabric
-
June
-
A. Kumar et al. Express virtual channels: Towards the ideal interconnection fabric. In ISCA, June 2007.
-
(2007)
ISCA
-
-
Kumar, A.1
-
15
-
-
70349752957
-
Dynamic and distributed multipath routing policy for high-speed cluster networks
-
Washington, DC, USA, IEEE Computer Society
-
D. Lugones, D. Franco, and E. Luque. Dynamic and distributed multipath routing policy for high-speed cluster networks. In CCGRID '09: Proceedings of the 2009 9th IEEE/ACM International Symposium on Cluster Computing and the Grid, pages 396-403, Washington, DC, USA, 2009. IEEE Computer Society.
-
(2009)
CCGRID '09: Proceedings of the 2009 9th IEEE/ACM International Symposium on Cluster Computing and the Grid
, pp. 396-403
-
-
Lugones, D.1
Franco, D.2
Luque, E.3
-
16
-
-
4644301652
-
Low-latency virtual-channel routers for on-chip networks
-
June
-
R. Mullins et al. Low-latency virtual-channel routers for on-chip networks. In ISCA, June 2004.
-
(2004)
ISCA
-
-
Mullins, R.1
-
17
-
-
0031246030
-
Fast, approximate synthesis of fractional gaussian noise for generating self-similar network traffic
-
V. Paxson. Fast, approximate synthesis of fractional gaussian noise for generating self-similar network traffic. SIGCOMM CCR., 27(5), 1997.
-
(1997)
SIGCOMM CCR
, vol.27
, Issue.5
-
-
Paxson, V.1
-
18
-
-
0000002112
-
The Cray T3E network: Adaptive routing in a high-performance 3D torus
-
S. L. Scott and G. Thorson. The Cray T3E network: Adaptive routing in a high-performance 3D torus. In Hot Interconnects-4, 1996.
-
(1996)
Hot Interconnects-4
-
-
Scott, S.L.1
Thorson, G.2
-
19
-
-
49249086142
-
Larrabee: A many-core x86 architecture for visual computing
-
L. Seiler et al. Larrabee: a many-core x86 architecture for visual computing. In SIGGRAPH, 2008.
-
(2008)
SIGGRAPH
-
-
Seiler, L.1
-
20
-
-
84955452760
-
Dynamic voltage scaling with links for power optimization of interconnection networks
-
Feb.
-
Li Shang, Li-Shiuan Peh, and Niraj K. Jha. Dynamic voltage scaling with links for power optimization of interconnection networks. In HPCA, Feb. 2003.
-
(2003)
HPCA
-
-
Shang, L.1
Peh, L.-S.2
Jha, N.K.3
-
21
-
-
78650477452
-
-
SPLASH-2. http://www-flash.stanford.edu/apps/SPLASH/.
-
SPLASH-2
-
-
-
22
-
-
0036505033
-
The Raw microprocessor: A computational fabric for software circuits and general-purpose programs
-
M.B. Taylor et al. The Raw microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE-MICRO, 2002.
-
(2002)
IEEE-MICRO
-
-
Taylor, M.B.1
-
23
-
-
0038041045
-
Throughput-centric routing algorithm design
-
June
-
Brian Towles and William J. Dally. Throughput-centric routing algorithm design. In SPAA, pages 200-209, June 2003.
-
(2003)
SPAA
, pp. 200-209
-
-
Towles, B.1
Dally, W.J.2
-
24
-
-
85025263656
-
Universal schemes for parallel communication
-
L. G. Valiant and G. J. Brebner. Universal schemes for parallel communication. In STOC, 1981.
-
(1981)
STOC
-
-
Valiant, L.G.1
Brebner, G.J.2
-
25
-
-
34548858682
-
An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS
-
S. Vangal et al. An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS. In ISSCC, 2007.
-
(2007)
ISSCC
-
-
Vangal, S.1
|