Pin-shape assessment for interlayer-cooled chip stacks with periodic boundary condition modeling

16th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2010

Volumn , Issue , 2010, Pages 266-275

  Töral, Gözde ^a   Bender, Roland ^c   Leblebici, Yusuf ^a   Brunschwiler, Thomas ^b  

^a EPFL   (Switzerland)

^b IBM RESEARCH ZURICH   (Switzerland)

^c ANSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE LAYER; CHARACTERISTIC PARAMETER; CLASSICAL APPROACH; CONTROL LOOP; CONVECTIVE ENERGY; FLUID BOUNDARY; FLUID CAVITIES; FLUID TEMPERATURES; FLUX RATIO; FORTRAN; HEAT REMOVAL; HIGH PERMEABILITY; HOT SPOT; HYDRODYNAMIC BOUNDARY CONDITIONS; INLET TEMPERATURE; JUNCTION TEMPERATURES; LIQUID PHASE; MODELING APPROACH; MULTISCALES; PARALLEL PLATES; PERIODIC BOUNDARY CONDITIONS; PIN-FINS; SOLID BOUNDARIES; SPEED-UP FACTORS; SUBDOMAIN; TEMPERATURE FIELD; TEMPERATURE INCREASE; THERMAL BOUNDARY CONDITIONS; THERMAL BUDGET; THERMAL RESISTANCE; THROUGH SILICON VIAS; UNIT CELLS;

BOUNDARY CONDITIONS; COMPUTATIONAL FLUID DYNAMICS; FLUID DYNAMICS; FLUIDS; HEAT CONVECTION; HEAT FLUX; HEAT RESISTANCE; HYDRODYNAMICS; RATING; THREE DIMENSIONAL;

TRANSPORT PROPERTIES;

EID: 78650440846     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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