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Volumn , Issue , 2008, Pages 1-6

Fault Tolerant Four-State Logic by Using Self-Healing Cells

Author keywords

[No Author keywords available]

Indexed keywords

DEADLOCK DETECTIONS; ERROR-PRONE; FAULT-TOLERANT; FEATURE SIZES; HIGH RELIABILITIES; HIGHER INTEGRATIONS; MULTIPLE FAULTS; OPERATING SPEED; SELF-HEALING; SPACE MISSIONS; SUPPLY VOLTAGES; TEMPORAL REDUNDANCIES;

EID: 78650422021     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751832     Document Type: Conference Paper
Times cited : (11)

References (17)
  • 1
    • 0026821315 scopus 로고
    • Four state asynchronous architectures
    • February
    • A. J. McAuley, "Four state asynchronous architectures," IEEE Transactions on Computers, vol. 41, no. 2, pp. 129-142, February 1992.
    • (1992) IEEE Transactions on Computers , vol.41 , Issue.2 , pp. 129-142
    • McAuley, A.J.1
  • 5
    • 4544302417 scopus 로고    scopus 로고
    • C. LaFrieda and R. Manohar, Fault detection and isolation techniques for quasi delay-insensitive circuits, in DSN '04: Proceedings of the 2004 International Conference on Dependable Systems\ and Networks (DSN'04). Washington, DC, USA: IEEE Computer Society, 2004, p. 41.
    • C. LaFrieda and R. Manohar, "Fault detection and isolation techniques for quasi delay-insensitive circuits," in DSN '04: Proceedings of the 2004 International Conference on Dependable Systems\ and Networks (DSN'04). Washington, DC, USA: IEEE Computer Society, 2004, p. 41.
  • 7
    • 33748557770 scopus 로고    scopus 로고
    • S. Peng and R. Manohar, Fault tolerant asynchronous adder through dynamic self-reconfiguration, in ICCD'05: Proceedings of the 2005 International Conference on Computer Design, 2005, pp. 171-179.
    • S. Peng and R. Manohar, "Fault tolerant asynchronous adder through dynamic self-reconfiguration," in ICCD'05: Proceedings of the 2005 International Conference on Computer Design, 2005, pp. 171-179.
  • 14
    • 62349083287 scopus 로고    scopus 로고
    • Design of an asynchronous processor based on code alternation logic - exploration of delay insensitivity,
    • Ph.D. dissertation, Vienna University of Technology
    • W. Huber, "Design of an asynchronous processor based on code alternation logic - exploration of delay insensitivity," Ph.D. dissertation, Vienna University of Technology, 2005.
    • (2005)
    • Huber, W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.