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Volumn 2005, Issue , 2005, Pages 171-178

Fault tolerant asynchronous adder through dynamic self-reconfiguration

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS MACHINERY; COMPUTER GRAPHICS; COMPUTER HARDWARE; FORMAL LOGIC; MATHEMATICAL MODELS;

EID: 33748557770     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.56     Document Type: Conference Paper
Times cited : (13)

References (20)
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    • Cornell University
    • S. Peng et al. Explicit constructions of fault-tolerant open linear arrays. Technical Report CSL-TR-2005-1044, Cornell University, 2005.
    • (2005) Technical Report , vol.CSL-TR-2005-1044
    • Peng, S.1
  • 5
    • 85018132173 scopus 로고
    • Edge fault tolerance in graphs
    • F. Haray et.al. Edge fault tolerance in graphs. Networks, 23:135-142, 1993.
    • (1993) Networks , vol.23 , pp. 135-142
    • Haray, F.1
  • 10
    • 38249028223 scopus 로고
    • Explicit construction of linear sized tolerant networks
    • N. Alon et.al. Explicit construction of linear sized tolerant networks. Discrete Math, 72(1): 15-19, 1988.
    • (1988) Discrete Math , vol.72 , Issue.1 , pp. 15-19
    • Alon, N.1
  • 14
    • 0032628982 scopus 로고    scopus 로고
    • An overview of manufacturing yield and reliability modeling for semiconductor products
    • W. Kuo et.al. An overview of manufacturing yield and reliability modeling for semiconductor products. Proceedings of the IEEE, 87(8), 1999.
    • (1999) Proceedings of the IEEE , vol.87 , Issue.8
    • Kuo, W.1
  • 15
    • 0016992757 scopus 로고    scopus 로고
    • A graph model for fault-tolerant computing systems
    • J. P. Hayes. A graph model for fault-tolerant computing systems. IEEE Trans. on Computers, 25(9), 1976.
    • IEEE Trans. on Computers , vol.25 , Issue.9 , pp. 1976
    • Hayes, J.P.1
  • 17
    • 0038111456 scopus 로고
    • Master's thesis, California Institute of Technology
    • A. M. Lines. Pipelined asynchronous circuits. Master's thesis, California Institute of Technology, 1995.
    • (1995) Pipelined Asynchronous Circuits
    • Lines, A.M.1
  • 18
    • 0003626762 scopus 로고
    • Synthesis of asynchronous VLSI circuits
    • California Institute of Technology
    • A. J. Martin. Synthesis of asynchronous VLSI circuits. Technical Report CS-TR-93-28, California Institute of Technology, 1993.
    • (1993) Technical Report , vol.CS-TR-93-28
    • Martin, A.J.1
  • 19
    • 0003133883 scopus 로고
    • Probabilistic logics and the synthesis of reliable organisms from unreliable components
    • C. E. Shannon and J. McCarthy, editors, Princeton University Press
    • J. Von Neumann. Probabilistic logics and the synthesis of reliable organisms from unreliable components. In C. E. Shannon and J. McCarthy, editors, Automata Studies. Princeton University Press, 1956.
    • (1956) Automata Studies
    • Von Neumann, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.