Improving fault tolerance by using reconfigurable asynchronous circuits

Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Volumn , Issue , 2008, Pages 267-270

  Friesenbichler, Werner ^a   Panhofer, Thomas ^a   Delvai, Martin ^b  

^a RUAG Aerospace Austria GmbH   (Austria)

^b VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; DELAY CIRCUITS; DESIGN; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRON TUBES; ERROR ANALYSIS; ERROR DETECTION; ERRORS; FAULT DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; NETWORKS (CIRCUITS); QUALITY ASSURANCE; RELIABILITY;

ELECTRONIC CIRCUITS; FAULT-TOLERANCE;

LOGIC CIRCUITS;

EID: 50649106677     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2008.4538799     Document Type: Conference Paper

References (7)

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4. B. Johnson, Design and Analysis of Fault Tolerant Digital Systems. Addision Wesley, 1989.
5. W. Jang and A. J. Martin, "Soft-error robustness in QDI circuits," in Workshop on System Effects of Logical Soft Errors - SELSE1, 2005.
6. C. LaFrieda and R. Manohar, "Fault detection and isolation techniques for quasi delay-insensitive circuits," in DSN '04: Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN'04). Washington, DC, USA: IEEE Computer Society, 2004, p. 41.
7. T. Panhofer and M. Delvai, "Self-healing circuits for space applications," in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL'07), August 2007, pp. 505-506.