Efficient failure detection in pipelined asynchronous circuits

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2005, Pages 484-493

  Peng, Song ^a   Manohar, Rajit ^a  

^a Cornell University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; ERROR DETECTION; FORMAL LOGIC; INTEGRATED CIRCUITS;

ASYNCHRONOUS CIRCUITS; CLOCKLESS SYSTEMS; SOFT ERRORS;

COMPUTER SYSTEM RECOVERY;

EID: 28444451858     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. International Technology Roadmap for Semiconductors. Semiconductor Industry Association, 2004.
2. I. David, R. Ginosar, and M. Yoeli. Self-timed is self-checking. Journal of Electronic Testing: Theory and Applications, 6(2), 1995.
3. P. E. Dodd and L. W. Massengill. Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Transactions on Nuclear Science, 50(3), 2003.
4. P. D. Hyde and G. Russell. A comparative study of the design of synchronous and asynchronous self-checking RISC processors. In Proceedings of IEEE International On-line Testing Symposium, 2004.
5. W. Jang and A. J. Martin. SEU-tolerant QDI circuits, In Proceedings of International Symposium on Asynchronous Circuits and Systems, 2005.
6. B. W. Johnson. Design and Analysis of Fault Tolerant Digital Systems. Addison Wesley, 1989.
7. C. LaFrieda and R. Manohar. Robust fault detection and tolerance in quasi delay-insensitive circuits. In Proceedings of International Conference on Dependable Systems and Networks, 2004.
8. A. Lines. Pipelined asynchronous circuits. Master's thesis, 1995.
9. N. R. Mahapatra, A. Tareen, and S.V. Garimella. Comparison and analysis of delay elements. In Proceedings of the 45th Midwest Symposium on Circuits and Systems, 2002.
10. A. J. Martin. Synthesis of asynchronous VLSI circuits. Technical Report CS-TR-93-28, 1993.
11. A. J. Martin, M. Nyström, and C. G. Wong. Three generations of asynchronous microprocessors. IEEE Design and Test of Computers, 20(6), 2003.
12. E. J. McCluskey and C. W. Tseng. Stuck-fault tests vs. actual defects. In Proceedings of International Test Conference, 2000.
13. G. McFarland. CMOS Technology Scaling and Its Impact on Cache Delay. PhD thesis, Stanford University, August 1997.
14. S. J. Piestrak and T. Nanya. Towards totally self-checking delay-insensitive systems. In Proceedings of International Symposium on Fault-Tolerant Computing, 1995.
15. D. A. Rennels and H. Kim. Concurrent error detection in self-timed VLSI. In Proceedings of International Symposium on Fault-Tolerant Computing, 1994.
16. G. L. Ries, G. S. Choi, and R. K. Iyer. Device-level transient fault modeling. In Proceedings of International Symposium on Fault-Tolerant Computing, 1994.
17. I. E. Sutherland and J. Ebergen. Computers without clocks. Scientific American, 2002.
18. T. Verdel and Y. Makris. Duplication-based concurrent error detection in asynchronous circuits: Short-comings and remedies. In Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002.
19. J. L. Yang, C. S. Choy, C. F. Chan, and K. P. Pun. Design for self-checking and self-timed datapath. In Proceedings of IEEE VLSI Test Symposium, 2003.