Asynchronous logic design - From concepts to implementation

CITSA 2006 - 3rd Int. Conf. on Cybernetics and Information Technol., Systems and Applications, Jointly with the 4th Int. Conf. on Computing, Communications and Control Technologies, CCCT 2006 - Proc.

Volumn 1, Issue , 2006, Pages 81-86

  Delvai, Martin ^a   Steininger, Andreas ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Asynchronous logic; Asynchronous processor; Delay insensitive design; Micro pipeline

Indexed keywords

CYBERNETICS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INFORMATION TECHNOLOGY;

ASYNCHRONOUS DESIGN; ASYNCHRONOUS LOGIC; ASYNCHRONOUS LOGIC DESIGN; ASYNCHRONOUS PROCESSORS; BASIC CONCEPTS; CONCEPT PAPERS; MICRO-PIPELINE; PRACTICAL INVESTIGATIONS;

FORMAL LOGIC;

EID: 48149091774     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. R. Bhamidipati, A. Zaidi, S. Makineni, K. K. Low, R. Vhen, K.-Y. Liu, and J. Dalgrehn. Challenges and Mothodologies for Implementing High-Performance Network Processors. Intel technology journal, vol. 06, issue 03, Intel Corporation, 2002.
2. M. Delvai. Design of an Asynchronous Processor Based on Code Alternation Logic - Treatment of Non-Linear Data Paths. PhD thesis, Vienna University of Technology, 2005.
3. M. Delvai, W. Huber, P. Puschner, and A. Steininger. Processor Support for Temporal Predictability - The SPEAR Design Example. In Proceedings of the 15th Eu-romicro Conference on Real-Time Systems, Porto, Portugal, July 2003.
4. K. M. Fant and S. A. Brandt. NULL Convention Logic: A Complete and Consistent Logic for Asynchronous Digital Circuit Synthesis. In Proc. International Conference on Application Specific Systems, Architectures and Processors, pages 261-273, august 1996.
5. E. Friedman. Clock distribution networks in synchronous digital integrated circuits. Proceedings of the IEEE, 89(5):665-692, 2001.
6. S. Hauck. Asynchronous design methodologies: An Overview. In Proceedings of the IEEE, volume 83, pages 69-93, 1995.
7. D. A. Huffman. The synthesis of sequential switching circuits. Journal of the Franklin Institute, March/April 1954.
8. International SEMATECH. International Technology Roadmap for Semiconductors, 2003 Edition. http://public.itrs.net/Files/2003ITRS/Home2003. htm, 2003. .
9. A. J. Martin. The limitations to delay-insensitivity in asynchronous circuits. In Proceedings of the sixth MIT conference on Advanced research in VLSI, pages 263-278. MIT Press, 1990.
10. A. McAuley. Four State Asynchronous Architectures. IEEE Transactions on Computers, Volume 41(Issue 2):129-142, 1992.
11. C. J. Myers. Asynchronous Circuit Design. John Wiley & Sons, inc., 2001.
12. P. J. Restle et al. A Clock Distribution Network for Microprocessors. IEEE Journal of Solid-State Circuits, 36(5), May 2001.
13. J. Sparso and S. Furber. Principles of Asynchronous Circuit Design. Dimes, 2001.
14. I. E. Sutherland. Micorpipelines. In Communications of the ACM, volume 32, pages 720 - 738, 1989.
15. H. Terada, S. Miyata, and M.Iwata. DDMP's: Self-timed super-pipelined data-driven multimedia processors. In IEEE, volume 87, pages 289-296,1999.