Affordable and process window increasing full chip ILT masks

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7823, Issue PART 1, 2010, Pages

  Xiao, Guangming ^a   Irby, Dave ^a   Cecil, Tom ^a   Kim, David ^a   Ohara, Shuichiro ^b   Aburatani, Isao ^b  

^a Luminescent Technologies Inc   (United States)

^b Nippon Control Systems Corporation   (Japan)

Author keywords

32nm below; E beam mask write time; E beam shot count; Inverse lithography technology (ILT); Low k1 lithography; Mask cost reduction; Resolution enhancement technology (RET); Sub resolution assist feature (SRAF)

Indexed keywords

E-BEAM MASK WRITE TIME; E-BEAM SHOT COUNT; INVERSE LITHOGRAPHY TECHNOLOGIES; LOW K1 LITHOGRAPHY; MASK COST REDUCTION; RESOLUTION ENHANCEMENT TECHNOLOGY; SUB-RESOLUTION ASSIST FEATURE;

COST REDUCTION; LITHOGRAPHY; TECHNOLOGY;

PHOTOMASKS;

EID: 78649837742     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.866131     Document Type: Conference Paper

References (8)

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6. Farys V. et al, "SRAF Enhancement using Inverse Lithography for 32 nm Hole Patterning and Beyond", Proc. of SPIE Vol. 7488 (2009)
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8. Xiao, G., et al, "E-beam writing time improvement for Inverse Lithography Technology mask for full-chip", Photomask and NGL Mask Technology XVII, 2010, Proc. of SPIE Vol. 7748 (2010)