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Volumn 7488, Issue , 2009, Pages

Inverse lithography (ILT) mask manufacturability for full-chip device

Author keywords

Inverse lithography technology (ILT); Lithography simulation; Resolution enhancement technology (RET); Sub resolution assist feature (SRAF)

Indexed keywords

CHIP-LEVEL; CLIP LEVEL; INVERSE LITHOGRAPHY; INVERSE LITHOGRAPHY TECHNOLOGY (ILT); LITHOGRAPHY SIMULATION; LOW K1 LITHOGRAPHY; MANUFACTURABILITY; MASK DATA; MASK PATTERNS; RESOLUTION ENHANCEMENT TECHNOLOGY (RET); SUB-RESOLUTION ASSIST FEATURE;

EID: 79959350656     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.833572     Document Type: Conference Paper
Times cited : (15)

References (4)
  • 3
    • 42149178602 scopus 로고    scopus 로고
    • Inverse lithography technology (ILT): Keep the balance between SRAF and MRC at 45 and 32nm
    • Pang, L., et al, "Inverse Lithography Technology (ILT): Keep the balance between SRAF and MRC at 45 and 32nm", Proc. SPIE 6730, (2007)
    • (2007) Proc. SPIE , vol.6730
    • Pang, L.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.