Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 520-523

  Sapatnekar, Sachin S ^a  

^a IOWA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; CRITICAL PATH ANALYSIS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; NUMERICAL ANALYSIS; QUEUEING THEORY; SEQUENTIAL CIRCUITS; VLSI CIRCUITS;

ALL PAIRS INPUT TO OUTPUT DELAYS; SYNCHRONOUS SEQUENTIAL CIRCUITS;

COMBINATORIAL CIRCUITS;

EID: 0029708044     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)