A 390MHz single-chip application and dual-mode baseband processor in 90nm triple-Vt CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages

  Ito, Masayuki ^a   Hattori, Toshihiro ^a   Irita, Takahiro ^a   Tatezawa, Ken ^a   Tanaka, Fumihito ^a   Hirose, Kenji ^a   Yoshioka, Shinichi ^a   Ohno, Koji ^a   Tsuchihashi, Reiko ^b   Sakata, Minoru ^c   Yamamoto, Masayuki ^d   Arai, Yuji ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NTT DOCOMO   (Japan)

^c Mitsubishi Electric ^*

^d SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER LAYERS; CODE DIVISION MULTIPLE ACCESS; ELECTRIC POWER UTILIZATION; PROGRAM PROCESSORS; SIGNAL PROCESSING;

CLOCK-STOP SCHEME; INTERCONNECT BUFFERS; WCDMA;

MICROPROCESSOR CHIPS;

EID: 34548855672     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373400     Document Type: Conference Paper

References (2)

1. T. Kamei, et al., "A Resume-Standby Application Processor for 3G Cellular Phones," ISSCC Dig. Tech. Papers, pp. 336-337, Feb., 2004.
2. T. Hattori, et al., "A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor," ISSCC Dig. Tech. Papers, pp. 542-543, Feb., 2006.