Arithmetic logic circuits using self-timed bit level dataflow and early evaluation

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 18-23

  Reese, Robert B ^a   Thornton, Mitch A ^a   Traver, Cherrice ^b  

^a MISSISSIPPI STATE UNIVERSITY   (United States)

^b UNION COLLEGE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DATA FLOW ANALYSIS; INTEGRATED CIRCUITS; ITERATIVE METHODS;

PHASED LOGIC (PL);

LOGIC CIRCUITS;

EID: 0035188663     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2001.954998     Document Type: Article

References (20)

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6. A self clocked FPGA for general purpose logic emulation
7. A theory of asynchronous circuits
8. A design of a fast and area efficient mult-input muller c-element
9. Micropipelines
10. Self-timed iteration
11. An FPGA for implementing asychronous circuits
12. Asynchronous design using commercial HDL synthesis tools
13. An evaluation of asynchronous addition
14. Design of a low-latency asynchronous adder using speculative completion