The core clock system on the next generation Itanium™ microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 146-147+453+137

  Anderson, Ferd E ^a   Wells, J Steve ^a   Berta, Eugene Z ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CACHE MEMORY; CAPACITANCE; COMPUTER SIMULATION; GRAPHICAL USER INTERFACES; HEURISTIC METHODS; MODULATION; PHASE LOCKED LOOPS; PRECISION ENGINEERING; TIMING CIRCUITS; TIMING JITTER;

CLOCK DISTRIBUTION;

MICROPROCESSOR CHIPS;

EID: 0036112361     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. The implementation of the next-generation 64 b itanium microprocessor
2. Clock generation and distribution for the first IA-64 microprocessor
3. A clock distribution network for microprocessors
4. Inductance calculation in a complex integrated circuit environment