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Volumn , Issue , 2002, Pages 255-259

Generalized early evaluation in self-timed circuits

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS CIRCUITS; BENCHMARK CIRCUIT; DESIGN STYLES; EARLY EVALUATION; GENERAL METHOD; GLOBAL CLOCKS; SELF-TIMED CIRCUITRY; SELF-TIMED CIRCUITS;

EID: 16444383993     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998281     Document Type: Conference Paper
Times cited : (9)

References (24)
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    • Benini, L.1    Macii, E.2    Poncino, M.3
  • 3
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    • Automatic synthesis of large telescopic units based on near-minimum timed supersetting
    • L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, and M. Poncino. Automatic synthesis of large telescopic units based on near-minimum timed supersetting. IEEE Trans. on Comp., 48(8):769-779, 1999.
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    • Benini, L.1    De Micheli, G.2    Lioy, A.3    Macii, E.4    Odasso, G.5    Poncino, M.6
  • 4
    • 0033328531 scopus 로고    scopus 로고
    • Averagecase technology mapping of asynchronous burstmode circuits
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    • Chou, W.-C.1    Beerel, P.A.2    Yun, K.Y.3
  • 9
    • 0001254304 scopus 로고
    • Self-timed iteration
    • In C. H. Sequin, editor, Elsevier Science Publishers
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  • 12
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    • (1996) Custom Integrated Circuits Conference , pp. 148-151
    • How, D.L.1
  • 15
    • 0030244752 scopus 로고    scopus 로고
    • Phased logic: Supporting the synchronous design paradigm with delayinsensitive circuitry
    • D. H. Linder and J. C. Harden. Phased logic: Supporting the synchronous design paradigm with delayinsensitive circuitry. IEEE Trans. on Comp., 45(9), 1996.
    • (1996) IEEE Trans. on Comp. , vol.45 , pp. 9
    • Linder, D.H.1    Harden, J.C.2
  • 17
    • 0030235195 scopus 로고    scopus 로고
    • Design of a low-latency asynchronous adder using speculative execution
    • S. M. Nowick. Design of a low-latency asynchronous adder using speculative execution. II Proc. Comput. Digit. The., 143(5):301-307, 1996.
    • (1996) II Proc. Comput. Digit. The. , vol.143 , Issue.5 , pp. 301-307
    • Nowick, S.M.1
  • 19
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    • Arithmetic logic circuits using self-timed bit-level dataflow and early evaluation
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    • Synthesis and simulation of phased logic systems
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.