Testing of asynchronous designs by "inappropriate" means. Synchronous approach

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2002, Pages 171-180

  Kondratyev, Alex ^a   Sorensen, Lief ^b   Streich, Amy ^b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b Theseus Logic Inc ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY;

'CURRENT; ASYNCHRONOUS CIRCUITS; ASYNCHRONOUS DESIGN; CAD TOOL; COMMERCIAL TOOLS; DESIGN TOOL; STUCK-AT FAULTS; SYNCHRONOUS CIRCUITS; TEST PATTERN GENERATIONS; TESTING METHODOLOGY;

COMPUTER AIDED DESIGN;

EID: 77957956590     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (29)

1. Shai Rotem, Ken Stevens, Ran Ginosar, Peter Beerel, Chris Myers, Kenneth Yun, Rakefet Kol, Charles Dike, Marly Roncken, and Boris Agapiev. RAPPID: An asynchronous instruction length decoder. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 60-70, April 1999.
2. Ivan Sutherland and Jon Lexau. Designing fast asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 184-193. IEEE Computer Society Press, March 2001.
3. Kees van Berkel, Ronan Burgess, Joep Kessels, Ad Peeters, Marly Roncken, and Frits Schalij. A fully-asynchronous low-power error corrector for the DCC player. In International Solid State Circuits Conference, pages 88-89, February 1994.
4. S. B. Furber, D. A. Edwards, and J. D. Garside. AMULET3: a 100 MIPS asynchronous embedded processor. In Proc. International Conf. Computer Design (ICCD), September 2000.
5. W.A. Lien, P. Day, C. Faransworth, D.L. Jackson, J. Liu, and N. Paver. Noise in a self-timed and synchronous implementation of a DSP. Unpublished, White Paper, Cogency Technology Inc., 1997.
6. John McCardle, David Chester. Measuring an Asynchronous Processor's Power and Noise, SNUG Conference, April 2001.
7. K.Y. Yun, D.L. Dill, and S.M. Nowick. Synthesis of 3D asynchronous state machines. In Proc. International Conf. Computer Design (ICCD), pages 346-350. IEEE Computer Society Press, October 1992.
8. Steven M. Nowick and David L. Dill. Automatic synthesis of locally clocked asynchronous state machine. In Proc. International Conf. Computer-Aided Design (ICCAD). IEEE Computer Society Press, pp.318-321, November 1991.
9. Alain J. Martin. Programming in VLSI: From communicating processes to delay-insensitive circuits. In C. A. R. Hoare, editor, Developments in Concurrency and Communication, UT Year of Programming Series pages 1-64. Addison-Wesley, 1990
10. K. van Berkel. Handshake Circuits: an Asynchronous Architecture for VLSI Programming, Cambridge University Press, 1993.
11. Tam-Anh Chu. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science, June 1987.
12. V.I. Varshavsky, editor. Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems. Kluwer Academic Publishers, Dordrecht, The Netherlands, 1990.
13. M. Renaudin, P. Vivet, and F. Robin. A design framework for asynchronous/synchronous circuits based on CHP to HDL translation. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 135-144, April 1999.
14. Ivan Blunno and Luciano Lavagno. Automated synthesis of micro-pipelines from behavioral Verilog HDL. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 84-92. IEEE Computer Society Press, April 2000.
15. Michiel Ligthart, Karl Fant, Ross Smith, Alexander Taubin, and Alex Kondratyev. Asynchronous design using commercial HDL synthesis tools. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 114-125. IEEE Computer Society Press, April 2000.
16. K. Fant and S.A. Brandt. NULL conventional logic: A complete and consistent logic for asynchronous digital circuit synthesis. In International Conference on Application-specific Systems, Architectures, and Processors, pages 261-273, 1996.
17. Peter Beerel and Teresa Meng. Semi-modularity and self-diagnostic asynchronous control circuits. In Carlo H. Sequin, editor, Advanced Research in VLSI, pages 103-117. MIT Press, March 1991.
18. Oriol Roig, Jordi Cortadella, Marco A. Pena, and Enric Pastor. Automatic generation of synchronous test patterns for asynchronous circuits In Proc. ACM/IEEE Design Automation Conference, pages 620-625, June 1997.
19. Ajay Khoche and Erik Brunvand. Testing self-timed circuits using scan paths. In 5th NASA Symposium on VLSI Design, November 1993.
20. O. A. Petlin and S. B. Furber. Scan testing of micropipelines. In Proc. IEEE VLSI Test Symposium, pages 296-301, May 1995.
21. Marly Roncken. Partial scan test for asynchronous circuits illustrated on a DCC error corrector. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 247-256, November 1994.
22. Marly Roncken. Defect-oriented testability for asynchronous IC's. Proceedings of the IEEE, 87(2):363-375, February 1999.
23. W. J. Bainbridge and S. B. Furber. Delay insensitive system-on-chip interconnect using 1-of-4 data encoding. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 118-126. IEEE Computer Society Press, March 2001.
24. K. Fant, R. Stephani, R. Smith, R. Jorgenson. The orphans in 2 value NULL convention logic. Theseus Logic, 1998, (http://www.theseus.com/PDF/orph-paper. pdf)
25. Alexander Saldanha, Robert Brayton, and Alberto Sangiovanni-Vincentelli. Equivalence of robust delay-fault and single stuck-fault test generation In Proc. ACM/IEEE Design Automation Conference, pages 173-176,1992.
26. M. Abramovici, M. Breuer, A. Friedman. Digital Systems Testing and Testable Design, Computer Science Press, 1990
27. D. Scherz, G. Metze. On the design of multiple fault diagnosable networks. IEEE Trans. Comput., vol. C-21, August, 1972
28. Pieter J. Hazewindus. Testing Delay-Insensitive Circuits. PhD thesis, California Institute of Technology, 1992.
29. E.B. Eichelberger and T.W. Williams. A logic design structure for LSI testability. Proc. ACM/IEEE Design Automation Conf., pages 462-486, 1977