Automatic generation of synchronous test patterns for asynchronous circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1997, Pages 620-625

  Roig, Oriol ^a   Cortadella, Jordi ^a   Pena, Marco A ^a   Pastor, Enric ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; FAILURE ANALYSIS; LOGIC GATES; MATHEMATICAL MODELS;

ASYNCHRONOUS CIRCUITS; AUTOMATIC TEST PATTERN GENERATION; SYNCHRONOUS CIRCUITS; SYNCHRONOUS FINITE STATE MACHINE;

INTEGRATED CIRCUIT TESTING;

EID: 0030703049     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/266021.266300     Document Type: Conference Paper

References (25)