A design framework for asynchronous/synchronous circuits based on CHP to HDL translation

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 1999, Pages 135-144

  Renaudin, M ^a   Vivet, P ^a,b   Robin, F ^a,c  

^a TIMA LABORATORY   (France)

^b ORANGE LABS   (France)

^c CSEM SA   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS CIRCUITS; COMMUNICATING SEQUENTIAL PROCESS; DESIGN FLOWS; DESIGN FRAMEWORKS; GATE LEVELS; ORIENTED FEATURES; SOFTWARE ENVIRONMENTS; SYNCHRONOUS CIRCUITS; TOPDOWN; VHDL PROGRAMS;

COMPUTER OPERATING PROCEDURES;

DESIGN;

EID: 3042647218     PISSN: 15228681     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1999.761529     Document Type: Conference Paper

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