Designing fast asynchronous circuits

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2001, Pages 184-192

  Sutherland, Ivan E ^a   Lexau, Jon K ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; CAPACITANCE; COMPUTER CIRCUITS; DELAY CIRCUITS; DESIGN; TIMING CIRCUITS; WIRE;

ASYNCHRONOUS CIRCUITS; ASYNCHRONY; CONTROL LOGIC; DESIGN-PROCESS; GATE DELAYS; LAY-OUT; TRADE OFF; TRANSISTOR WIDTH; WIRE CAPACITANCE; WIRE LENGTH;

LOGIC GATES;

EID: 33751178763     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2001.914082     Document Type: Conference Paper

References (7)

1. W. S. Coates, J. K. Lexau, I. W. Jones, S. M. Fairbanks and I. E. Sutherland, "FLEETzero: An Asynchronous Switching Experiment," Proc. of the Seventh International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2001.
2. J. Ebergen, "Squaring the FIFO in GasP," Proc. of the Seventh International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2001.
3. V. Narayanan, B. A. Chappell, and B. M. Fleischer, "Static Timing Analysis for Self Resetting Circuits," Proc. of the International Conference on Computer-Aided Design, 1996.
4. Proebsting, private communication.
5. Proebsting, US Patent 5,343,090, "Speed Enhancement Technique for CMOS Circuits," August 30, 1994.
6. I. Sutherland and S. Fairbanks, "GasP: A Minimal FIFO Control," Proc. of the Seventh International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2001.
7. I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann Publishers, Inc., 1999.