Electrical TCAD simulations of a germanium pMOSFET technology

IEEE Transactions on Electron Devices

Volumn 57, Issue 10, 2010, Pages 2539-2546

  Hellings, Geert ^a,b   Eneman, Geert ^a,b   Krom, Raymond ^a,b   De Jaeger, Brice ^a   Mitard, Jérôme ^a   De Keersgieter, An ^a   Hoffmann, Thomas ^a   Meuris, Marc ^a   De Meyer, Kristin ^a,b  

^a IMEC   (Belgium)

^b Katholieke Universiteit Leuven   (Belgium)

Author keywords

Germanium; modeling; MOSFET; technology computer aided design (TCAD) simulations

Indexed keywords

BAND TO BAND TUNNELING; BIAS CONDITIONS; COMMERCIAL TECHNOLOGY; DEVICE SIMULATORS; ELECTRICAL SIMULATION; GATE LENGTH; IMPURITY SCATTERING; MOBILITY MODEL; MOBILITY REDUCTION; MODELING; MOS-FET; P-MOSFETS; PMOSFET; TCAD SIMULATION; TECHNOLOGY COMPUTER-AIDED DESIGN (TCAD) SIMULATIONS; TRANSVERSAL FIELD; TRAP ASSISTED TUNNELING;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; GERMANIUM; TECHNOLOGY;

MOSFET DEVICES;

EID: 77957014490     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2060726     Document Type: Article

References (28)

1. D. Brunco, B. De Jaeger, G. Eneman, J. Mitard, G. Hellings, A. Satta, V. Terzieva, L. Souriau, F. Leys, G. Pourtois, M. Houssa, G. Winderickx, E. Vrancken, S. Sioncke, K. Opsomer, G. Nicholas, M. Caymax, A. Stesmans, J. Van Steenbergen, P. Mertens, M. Meuris, and M. Heyns, "Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performance," J. Electrochem. Soc., vol.155, no.7, pp. H552-H561, 2008.
2. K. C. Saraswat, C. O. Chui, T. Krishnamohan, A. Nayfeh, and P. McIntyre, "Ge based high performance nanoscale MOSFETs," Microelectron. Eng., vol.80, pp. 15-21, Jun. 2005, 14th biennial Conference on Insulating Films on Semiconductors.
3. E. Batail, S. Monfray, C. Tabone, O. Kermarrec, J. Damlencourt, P. Gautier, G. Rabille, C. Arvet, N. Loubet, Y. Campidelli, J. Hartmann, A. Pouydebasque, V. Delaye, C. Le Royer, G. Ghibaudo, T. Skotnicki, and S. Deleonibus, "Localized ultra-thin GeOI: An innovative approach to germanium channel MOSFETs on bulk Si substrates," in IEDM Tech. Dig., Dec. 2008, pp. 1-4.
4. G. Hellings, J. Mitard, G. Eneman, B. De Jaeger, D. Brunco, D. Shamiryan, T. Vandeweyer, M. Meuris, M. Heyns, and K. De Meyer, "High performance 70-nm germanium pMOSFETs with boron LDD implants," IEEE Electron Device Lett., vol.30, no.1, pp. 88-90, Jan. 2009.
5. Synopsys, Inc., Mountain View, CA, C-2009.06 ed. Sentaurus Device Reference Manual, 2009.
6. B. De Jaeger, R. Bonzom, F. Leys, O. Richard, J. Van Steenbergen, G. Winderickx, E. Van Moorhem, G. Raskin, F. Letertre, T. Billon, M. Meuris, and M. Heyns, "Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-on-insulator substrates," Microelectron. Eng., vol.80, pp. 26-29, Jun. 2005, 14th biennial Conference on Insulating Films on Semiconductors.
7. G. Eneman, B. De Jaeger, E. Simoen, D. Brunco, G. Hellings, J. Mitard, K. De Meyer, M. Meuris, and M. Heyns, "Quantification of drain extension leakage in a scaled bulk germanium pMOS technology," IEEE Trans. Electron Devices, vol.56, no.12, pp. 3115-3122, Dec. 2009.
8. G. Eneman, M. Wiot, A. Brugere, O. Casain, S. Sonde, D. Brunco, B. De Jaeger, A. Satta, G. Hellings, K. De Meyer, C. Claeys, M. Meuris, M. Heyns, and E. Simoen, "Impact of donor concentration, electric field, and temperature effects on the leakage current in germanium p+/n junctions," IEEE Trans. Electron Devices, vol.55, no.9, pp. 2287-2296, Sep. 2008.
9. E. Gaubas, M. Bauza, A. Uleckas, and J. Vanhellemont, "Carrier lifetime studies in Ge using microwave and infrared light techniques," Mater. Sci. Semicond. Process., vol. 9, no. 4/5, pp. 781-787, Aug.-Oct. 2006.
10. G. Hurkx, D. Klaassen, and M. Knuvers, "A new recombination model for device simulation including tunneling," IEEE Trans. Electron Devices, vol.39, no.2, pp. 331-338, Feb. 1992.
11. A. Schenk, "Rigorous theory and simplified model of the band-to-band tunneling in silicon," Solid State Electron., vol.36, no.1, pp. 19-34, Jan. 1993.
12. Synopsys, Inc., Mountain View, CA, C-2009.06 ed. Sentaurus Process Reference Manual, 2009.
13. D. Caughey and R. Thomas, "Carrier mobilities in silicon empirically related to doping and field," Proc. IEEE, vol.55, no.12, pp. 2192-2193, Dec. 1967.
14. C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.7, no.11, pp. 1164-1171, Nov. 1988.
15. G. Masetti, M. Severi, and S. Solmi, "Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon," IEEE Trans. Electron Devices, vol.ED-30, no.7, pp. 764-769, Jul. 1983.
16. V. I. Fistul, M. I. Iglitsyn, and E. M. Omelyanovskii, "Mobility of electrons in germanium strongly doped with arsenic," Sov. Phys.-Solid State, vol.4, no.4, pp. 784-785, 1962.
17. O. Golikova, B. Moizhes, and L. Stil'bans, "Hole mobility of germanium as a function of concentration and temperature," Sov. Phys.-Solid State, vol.3, no.10, pp. 2259-2265, 1962.
18. E. J. Ryder, "Mobility of holes and electrons in high electric fields," Phys. Rev., vol.90, no.5, pp. 766-769, Jun. 1953.
19. R. D. Larrabee, "Drift velocity saturation in p-type germanium," J. Appl. Phys., vol.30, no.6, pp. 857-859, Jun. 1959.
20. S. M. Sze, Physics of Semiconductor Devices. Hoboken, NJ: Wiley, 1981.
21. L. Trojman, L. Pantisano, M. Dehan, I. Ferain, S. Severi, H. E. Maes, and G. Groeseneken, "Velocity and mobility investigation in 1-nm-EOT HfSiON on Si (110) and (100)-Does the dielectric quality matter?" IEEE Trans. Electron Devices, vol.56, no.12, pp. 3009-3017, Dec. 2009.
22. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFETs: Part I-Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol.41, no.12, pp. 2357-2362, Dec. 1994.
23. J. Mitard, C. Shea, B. De Jaeger, A. Pristera, G. Wang, M. Houssa, G. Eneman, G. Hellings, W.-E. Wang, J. Lin, F. Leys, R. Loo, G. Winderickx, E. Vrancken, A. Stesmans, K. De Meyer, M. Caymax, L. Pantisano, M. Meuris, and M. Heyns, "Impact of EOT scaling down to 0.85 nm on 70 nm Ge-pFETs technology with STI," in VLSI Symp. Tech. Dig., Jun. 2009, pp. 82-83.
24. C. O. Chui, H. Kim, D. Chi, B. Triplett, P. McIntyre, and K. Saraswat, "A sub-400 ?C germanium MOSFET technology with high-? dielectric and metal gate," in IEDM Tech. Dig., 2002, pp. 437-440.
25. F. Bellenger, M. Houssa, A. Delabie, V. Afanasiev, T. Conard, M. Caymax, M. Meuris, K. De Meyer, and M. M. Heyns, "Passivation of Ge(100)/ GeO2/high-kappa gate stacks using thermal oxide treatments," J. Electrochem. Soc., vol.155, no.2, pp. G33-G38, 2008.
26. K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. Heyns, T. Krishnamohan, K. Saraswat, H. Maes, and G. Groeseneken, "On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates," IEEE Trans. Electron Devices, vol.55, no.2, pp. 547-556, Feb. 2008.
27. G. Hellings, E. Rosseel, T. Claryssea, D. Petersen, O. Hansen, P. Nielsen, E. Simoen, G. Eneman, B. De Jaeger, T. Hoffmann, K. De Meyer, and W. Vandervorst, "Systematic study of shallow junction formation on germanium substrates," Microelectron. Eng., 2010, to be published.
28. G. Du, X. Y. Liu, Z. L. Xia, Y. K. Wang, D. Q. Hou, J. F. Kang, and R. Q. Han, "Evaluations of scaling properties for Ge on insulator MOSFETs in nano-scale," Jpn. J. Appl. Phys., vol. 44, no. 4B, pp. 2195- 2197, Apr. 2005.