Ge based high performance nanoscale MOSFETs

Microelectronic Engineering

Volumn 80, Issue SUPPL., 2005, Pages 15-21

  Saraswat, Krishna C ^a   Chui, Chi On ^a   Krishnamohan, Tejas ^a   Nayfeh, Ammar ^a   McIntyre, Paul ^a  

^a Stanford University   (United States)

Author keywords

CMOS; Germanium; Heterostructure; High k dielectrics

Indexed keywords

CARRIER MOBILITY; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC POTENTIAL; ELECTRODES; GATES (TRANSISTOR); HETEROJUNCTIONS; SEMICONDUCTING GERMANIUM;

FABRICATION TECHNOLOGY; GATE ELECTRODES; HIGH-K DIELECTRICS;

MOSFET DEVICES;

EID: 19944393250     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2005.04.038     Document Type: Conference Paper

References (21)

1. The International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2001. (http://public.itrs.net/).
2. C. Choi, Modeling of Nanoscale MOSFETs (doctoral dissertation), Stanford University, 2002.
3. M. Lundstrom "Elementary scattering theory of the Si MOSFET" IEEE Electron Device Lett. 1997 361 363
4. M. Lundstrom, and Z. Ren "Essential physics of carrier transport in nanoscale MOSFETs" IEEE Trans. Electron Devices 2002 133 141
5. A. Lochtefeld, and D.A. Antoniadis "On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit?" IEEE Electron Device Lett. 2001 95 97
6. A. Lochtefeld, and D.A. Antoniadis "Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress" IEEE Electron Device Lett. 2001 591 593
7. M. Lundstrom "On the mobility versus drain current relation for a nanoscale MOSFET" IEEE Electron Device Lett. 2001 293 295
8. C.O. Chui, H. Kim, P.C. McIntyre, and K.C. Saraswat "A germanium NMOSFET process integrating metal gate and improved hi-k dielectrics" IEEE International Electron Devices Meeting (IEDM) Tech. Digest 2003 437 440
9. J. Bardeen, and W.H. Brattain "The transistor, a semi-conductor triode" Phys. Rev. 1948 230 231
10. H. R. Huff, "From the lab to the fab: transistors to integrated circuits," Proc 2003 International Conference on Characterization and Metrology for ULSI Technology., (2003) 3-39.
11. T. Krishnamohan, C. Jungemann and K. C. Saraswat, "A novel, very high performance, sub-20nm Depletion-Mode Double-Gate (DMDG) Si/SixGe(1-x)/Si channel PMOSFET", IEEE International Electron Devices Meeting (IEDM) 2003 Technical Digest, Washington, D.C. (2003) 687-690.
12. A. Nayfeh, C.O. Chui, K.C. Saraswat, and T. Yonehara "Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality" Appl. Phys. Lett. 85 14 2004 2815 2817
13. A. Nayfeh, C. O. Chui, K. C. Saraswat and T. Yonehara, "Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si," IEEE Electron Device Lett., (Accepted).
14. C.O. Chui, H. Kim, P.C. McIntyre, and K.C. Saraswat "Atomic Layer Deposition of High-k Dielectric for germanium MOS applications substrate surface preparation" IEEE Electron Dev. Lett. 25 2004 274 276
15. C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, "A Germanium NMOSFET Process Integrating Metal Gate and Improved Hi-k Dielectrics," IEEE Int. Electron Dev. Meet. 2003 Technical Digest, Washington, DC, (2003) 437-440.
16. C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "A Sub-400 °C Germanium MOSFET Technology with High-k Dielectric and Metal Gate," IEEE Int. Electron Dev. Meet. 2002 Technical Digest, San Francisco, CA, (2002) 437-440.
17. C. H. Huang, et al., VLSI Symp. Tech. Dig., (2003) 119.
18. A. Ritenour, et al., IEEE Int. Electron Dev. Meet. Tech. Digest, (2003) 433.
19. 2 gate dielectrics" Appl Phys. Lett. 83 2003 2432 2434
20. D. S. Yu1, et al., "3D GOI CMOSFETs with Novel IrO2(Hf) Dual Gates and High-κ Dielectric on 1P6M-0.18m-CMOS," IEEE Int. Electron Dev. Meet. 2002 Technical Digest, San Francisco, CA, (2004) 437-440.
21. T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi and K. C. Saraswat, "Low Defect Ultra-thin Fully Strained-Ge MOSFET on Relaxed Si with High Mobility and Low Band-To-Band-Tunneling (BTBT)," VLSI Technology Symp. Kyoto, (2005)