Voltage and frequency island optimizations for many-core/networks-on-chip designs

1st International Conference on Green Circuits and Systems, ICGCS 2010

Volumn , Issue , 2010, Pages 217-220

  Jang, Wooyoung ^a   Ding, Duo ^a   Pan, David Z ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORE LEVELS; ELECTRONIC SYSTEM LEVEL; LOW POWER; MANY-CORE; NETWORKS ON CHIPS; NOC DESIGN; ON-CHIP DESIGNS; POWER CONSUMPTION; POWER MANAGEMENTS; RESEARCH CHALLENGES;

ENERGY MANAGEMENT; OPTIMIZATION;

DESIGN;

EID: 77956572893     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICGCS.2010.5543066     Document Type: Conference Paper

References (36)

1. Luca Benini and Giovanni De Micheli, "Network on chips: a new SoC paradigm," Computer, 2002, 35, pp. 70-78.
2. William J. Dally and Brian Towles, "Route packets, not wires: on-chip interconnection networks," in Proc. Design Automation Confence, 2001.
3. D. E. Lackey et al., "Managing power and performance for system-on-chip designs using voltage islands," in Proc. International Conference on Computer-Aided Design, 2002
4. Intel, "Intel XScale core," http://www.intel.com.
5. AMD, "Mobile AMD Athon 4 processor model 6," http://www.amd.com.
6. IBM, "IBM ASIC Solutions," http://www.ibm.com.
7. M. Fleischmann, "Longrun power management - dynamic power management for Crusoe processors," http://www.transmeta.com.
8. D. M. Chapiro, "Globally asynchronous locally synchronous systems," PhD. dissertation, Dept. of Computer Science, Stanford University, Stanford, CA, 1984.
9. Jens Muttersbach, Thomas Villager and Wolfgang Fichtner, "Practical design of globally asynchronous locally synchronous systems," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2000.
10. Tiberiu Chelcea and Steven M. Nowick, "A low latency FIFO for mixed-clock system," in Proc. IEEE Computer Society Annual Workshop on VLSI, 2000.
11. Puru Choudhary and Diana Marculescu, "Hardware based frequency/voltage control of voltage frequency island systems," in Proc. International Conference on Hardware/Software Codesign and System Synthesis, 2006.
12. G. Quan and X. S. Hu, "Minimum energy fixed-priority scheduling for variable voltage processors," in Proc. Design, Automation and Test in Europe, 2002.
13. D. Shin, J. Kim and S. Lee, "Low-energy intra-task voltage scheduling using static timing analysis," in Proc. Desing Automation Conference, 2001.
14. Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil Dutt, Alex Veidenbaum, Alex Nicolau, "Profile-based dynamic voltage schedling using program checkpoints," in Proc. Design, Automation and Test in Europe, 2002.
15. Diana Marculescu, On the sue of microarchitecture-driven dynamic voltage scaling," in Workshop on Complexity-Effecitve Design, 2000.
16. Soray Ghiasi, Jason Casmira and Dirk Grunwald, "Uisng IPC variation in workloads with externally specified rates to reduce power consumption," in Workshop on Complexity-Effecitve Design, 2000.
17. K. Choi, R. Soma and M. Pedram, "Dynamic voltage and frequency scaling based on workload decomposition," in Proc. International Symposium on Low Power Electrics and Design, 2004.
18. Gaurav Dhiman and Tajana S. Rosing, "Dynamic voltage frequency scaling for multi-tasking systems using online learning," in Proc. International Symposium on Low Power Electrics and Design, 2007.
19. P. Juang, Q. Wu, L.-S. Peh, M. Martonosi and D. W. Clark, "Corrdinated, distributed, formal energy management of chip multiprocessors," in Proc. International Symposium on Low Power Electrics and Design, 2005.
20. C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose and M. Martonosi, "An analysis of efficient multi-core global power management policies: maximizing performance for a given power budget," in Proc. International Symposium on Microarchitecture, 2006.
21. Sebastian Herbert and Diana Marculescu, "Analysis of dynamic voltage/frequency scaling in chip-multiprocessors," in Proc. International Symposium on Low Power Electrics and Design, 2007.
22. J. Hu, Y. Shin, N. Dhanwada and R. Marculescu, "Architecting voltage islands in core-based system-on-a-chip designs," in Proc. International Symposium on Low Power Electrics and Design, 2004.
23. Huaizhi Wu, I-Min Liu, Martin D.F. Wong and Yusu Wang, "Post-placement voltage island generation under performance requirement," in Proc. International Conference on Computer-Aided Design, 2005
24. Umit Y. Ogras, Radu Marcuescu, Puru Choudhary and Diana Marculescu, "Voltage-frequency island partitioning for GALS-based networks-on-chip, " in Proc. Design Automation Conference, 2007.
25. Lap-Fai Leung and Chi-Ying Tsui, "Energy-aware synthesis of networks-on-chip implemented with voltage Islands," in Proc. Design Automation Conf., 2007.
26. Wooyoung Jang, Duo Ding and David Z. Pan, "A voltage-freqnecy island aware energy optimization framework for networks-on-chip," in Proc. International Conference on Computer-Aided Design, 2008.
27. W.-L. Hung, G.M. Link, Y. Xie, N. Vijaykrishnan, N. Dhanwada and J. Conner, "Temperature-aware voltage island architecturing in system-on-chip design," in Proc. International Conference on Computer Design, 2005.
28. Min Bao, Alexandru Andrei, Petru Eles and Zebo Peng, "On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration," in Proc. Design Automation Conference, 2009.
29. S. Herbert and D. Marculescu, "Variation-aware dynamic votlage/frequency scaling," in Proc. High Performance Computer Architecture, 2009.
30. S. Garg, D. Marculescu, R. Marculescu and U. Ogras, "Technology- driven on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective," in Proc. Design Automation Conference, 2009.
31. R. Puri, L. Stok, J. Cohn, D. Dung, D. Pan, D. Sylvester, A. Srivastava, "Pushing ASIC performance in a power envelope," in Proc. Design Automation Conference, 2003.
32. Y. Vlasov, "Silicon photonics for next generation computing systems," in European Conference on Optical Communications, 2008.
33. David A.B. Miller, "Device requirement for optical interconnects to silicon chips," in Proc. IEEE Special Issue on Silicon Photonics, 2009.
34. Assaf Shacham, Keren Bergman and Luca P. Carloni, "The case for low-power photonic networks on chip," in Proc. Design Automation Conference, 2007.
35. Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen and David Z. Pan, "O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration," In Proc. Design Automation Conf., 2009.
36. J. Chan, G. Hendry, A. Biberman, K. Bergman and L.P. Carloni, "PhoenixSim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks," in Prof. Design, Automation and Test in Europe, 2010.