Combining mapping and partitioning exploration for NoC-based embedded systems

Journal of Systems Architecture

Volumn 56, Issue 7, 2010, Pages 223-232

  Le Beux, Sébastien ^a   Bois, Guy ^a   Nicolescu, Gabriela ^a   Bouchebaba, Youcef ^b   Langevin, Michel ^b   Paulin, Pierre ^b  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b STMICROELECTRONICS   (Canada)

Author keywords

Application mapping; Hardware software partitioning; Multiobjective optimization; Network on Chip; System on Chip

Indexed keywords

APPLICATION MAPPING; EXECUTION PERFORMANCE; HARDWARE-SOFTWARE PARTITIONING; HARDWARE/SOFTWARE PARTITION; MULTI OBJECTIVE EVOLUTIONARY ALGORITHMS; MULTIMEDIA APPLICATIONS; NETWORK ON CHIP; NETWORKS ON CHIPS; NOC DESIGN; PIPELINE EXECUTION; SCALABLE COMMUNICATION; SOC ARCHITECTURE; STREAMING APPLICATIONS; SYSTEM ON CHIPS; SYSTEMS ON CHIPS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; EVOLUTIONARY ALGORITHMS; MAPPING; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; ROUTERS; SERVERS; VLSI CIRCUITS;

MULTIOBJECTIVE OPTIMIZATION;

EID: 77955716673     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2010.03.005     Document Type: Article

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