Optimizing configuration and application mapping for MPSoC architectures

Proceedings - 2009 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009

Volumn , Issue , 2009, Pages 474-481

  Le Beux, Sébastien ^a   Nicolescu, Gabriela ^a   Bois, Guy ^a   Bouchebaba, Youcef ^b   Langevin, Michel ^b   Paulin, Pierre ^b  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION MAPPING; CONFIGURABLE; COST REQUIREMENTS; EXECUTION PERFORMANCE; IMAGE PROCESSING APPLICATIONS; MULTI OBJECTIVE EVOLUTIONARY ALGORITHMS; MULTI-PROCESSORS; NETWORKS ON CHIPS; NOC DESIGN; PIPELINE EXECUTION; RING TOPOLOGY; SCALABLE COMMUNICATION; STREAMING APPLICATIONS; SYSTEMS ON CHIPS;

ELECTRIC NETWORK TOPOLOGY; EVOLUTIONARY ALGORITHMS; IMAGE PROCESSING; MAPPING; MICROPROCESSOR CHIPS;

COMPUTER ARCHITECTURE;

EID: 72849127387     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHS.2009.35     Document Type: Conference Paper

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