Fast copper plating process for TSV fill

Proceedings of Technical Papers - 2007 International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT

Volumn , Issue , 2007, Pages 219-222

  Zhang, Yun ^a   Richardson, Thomas ^a   Chung, Stream ^a   Wang, Chen ^a   Kim, Bioh ^a   Rietmann, Christian ^a  

^a Enthone Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COPPER ALLOYS; COPPER PLATING; ELECTROCHEMISTRY; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTROPLATING; METALLIZING; MICROSYSTEMS; NONMETALS; SILICON; TECHNOLOGY;

CHIP-TO-CHIP INTERCONNECTIONS; CU DAMASCENE; DEFECT-FREE; DEPTH CHANGES; FILL TIME; FUNCTIONAL DEVICES; IC PACKAGING; PLATING PROCESSES; SILICON-BASED TECHNOLOGIES; SUB MICRONS; THROUGH SILICON VIA;

COPPER;

EID: 48649091630     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMPACT.2007.4433603     Document Type: Conference Paper

References (2)

1. Eric Mounier, Market Drivers for 3D Integration, SEMICON West 2007, July 2007.
2. Y. Zhang and S. Chung, Defect Free TSV Fill with Minimum Overburden, IMAPS Device Packaging Conference, March 2007.