Evolution of organic chip packaging technology for high speed applications

IEEE Transactions on Advanced Packaging

Volumn 27, Issue 1, 2004, Pages 4-9

  Klink, Erich ^a   Garben, Bernd ^a   Huber, Andreas ^a   Kaller, Dierk ^a   Grivet Talocia, Stefano ^b   Katopis, George A ^c  

^a IBM   (Germany)

^b POLITECNICO DI TORINO   (Italy)

^c IBM   (United States)

Author keywords

HDI; MCM; SCM

Indexed keywords

ETCHING; FLIP CHIP DEVICES; INTEGRATED CIRCUITS; MULTICHIP MODULES;

HIGH DENSE INTERCONNECT; ORGANIC CHIP PACKAGING; POWER NOISE ANALYSIS; SINGLE-CHIP MODULE;

ELECTRONICS PACKAGING;

EID: 2442573799     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2004.825457     Document Type: Article

References (3)

1. R. R. Tummala, Microsystem Packaging. New York: McGraw-Hill, 2001, p. 321.
2. T. Winkel, D. Kaller, and A. Huber, "Determination of critical line length for on-chip interconnects for the future technologies as predicted in the SIA roadmap," in Proc. 4th IEEE Workshop Signal Propagat. Interconnects, 2000.
3. S. N. Towle et al., "Bumpless build-up layer packaging," in Proc. ASME Int. Mech. Eng. Congr. Expo. (IMECE), New York, Nov., 2001.