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Volumn , Issue , 2009, Pages 360-364

Characterization of MOS transistor after through-hole electrode fabrication and 3D-assembly by mechanical caulking

Author keywords

[No Author keywords available]

Indexed keywords

3D PACKAGING; 65-NM-NODE; ALUMINUM ELECTRODES; CHIP-TO-CHIP INTERCONNECTIONS; CONNECTING POINTS; ELECTRICAL INTERCONNECTIONS; ELECTRODE FABRICATION; ELECTRODE STRUCTURE; ETCHING RATE; ETCHING TIME; HIGH PERFORMANCE SYSTEMS; INTERLAYER DIELECTRIC FILMS; METAL LAYER; MOS TRANSISTORS; OVER-ETCHING; PRESSING LOADS; PRODUCTION TOLERANCE; ROOM TEMPERATURE; SATURATION CURRENT; STUD-BUMPS; SYSTEM-IN-PACKAGE APPLICATIONS; TEST ELEMENT GROUPS; THREE-DIMENSIONAL (3D) PACKAGING; THROUGH HOLE; TRANSISTOR CHARACTERISTICS; WIRE BONDING;

EID: 70349695889     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074041     Document Type: Conference Paper
Times cited : (4)

References (5)
  • 3
    • 24644516719 scopus 로고    scopus 로고
    • Optimization for chip stack in 3-D packaging
    • K. Hara et al: "Optimization for Chip Stack in 3-D Packaging" IEEE Transactions on advanced packaging, Vol.28, No.3, 2005, pp. 367-375.
    • (2005) IEEE Transactions on advanced packaging , vol.28 , Issue.3 , pp. 367-375
    • Hara, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.