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Volumn , Issue , 2009, Pages 360-364
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Characterization of MOS transistor after through-hole electrode fabrication and 3D-assembly by mechanical caulking
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Author keywords
[No Author keywords available]
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Indexed keywords
3D PACKAGING;
65-NM-NODE;
ALUMINUM ELECTRODES;
CHIP-TO-CHIP INTERCONNECTIONS;
CONNECTING POINTS;
ELECTRICAL INTERCONNECTIONS;
ELECTRODE FABRICATION;
ELECTRODE STRUCTURE;
ETCHING RATE;
ETCHING TIME;
HIGH PERFORMANCE SYSTEMS;
INTERLAYER DIELECTRIC FILMS;
METAL LAYER;
MOS TRANSISTORS;
OVER-ETCHING;
PRESSING LOADS;
PRODUCTION TOLERANCE;
ROOM TEMPERATURE;
SATURATION CURRENT;
STUD-BUMPS;
SYSTEM-IN-PACKAGE APPLICATIONS;
TEST ELEMENT GROUPS;
THREE-DIMENSIONAL (3D) PACKAGING;
THROUGH HOLE;
TRANSISTOR CHARACTERISTICS;
WIRE BONDING;
ALUMINA;
ALUMINUM;
BONDING;
CHIP SCALE PACKAGES;
DIELECTRIC DEVICES;
DIELECTRIC FILMS;
ELECTRONIC EQUIPMENT MANUFACTURE;
ETCHING;
FABRICATION;
GOLD;
MICROPROCESSOR CHIPS;
STUDS (STRUCTURAL MEMBERS);
TECHNOLOGY;
THREE DIMENSIONAL;
TRANSISTOR TRANSISTOR LOGIC CIRCUITS;
TRANSISTORS;
WAFER BONDING;
WIRE PRODUCTS;
ELECTRODES;
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EID: 70349695889
PISSN: 05695503
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ECTC.2009.5074041 Document Type: Conference Paper |
Times cited : (4)
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References (5)
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