A scalable circuit-architecture co-design to improve memory yield for high-performance processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 8, 2010, Pages 1209-1219

  Ndai, Patrick ^a   Goel, Ashish ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Architecture; circuit; decouple read stability and writeability; SRAM; yield

Indexed keywords

ARCHITECTURAL MODIFICATION; CELL DESIGN; CIRCUIT; CIRCUIT LEVELS; CO-DESIGNS; HIGH PERFORMANCE PROCESSORS; HIGH-PERFORMANCE MICROPROCESSORS; MEMORY YIELD; PARAMETRIC FAILURE; PERFORMANCE IMPACT; READ OPERATION; READ STABILITY; SMALL SIZE; SRAM CELL; WRITE OPERATIONS; YIELD ENHANCEMENT;

ARCHITECTURE; COMPUTER ARCHITECTURE; DESIGN; FUZZY CONTROL; MICROPROCESSOR CHIPS; STABILITY;

STATIC RANDOM ACCESS STORAGE;

EID: 77955175302     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2022628     Document Type: Article

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