Performance analysis of on-chip cache and main memory compression systems for high-end parallel computers

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'04

Volumn 1, Issue , 2004, Pages 469-475

  Yim, Keun Soo ^a   Kim, Jihong ^a   Koh, Kern ^a  

^a Seoul National University   (South Korea)

Author keywords

Cache and memory compression; I O bottleneck; Memory hierarchy; Performance evaluation; Processor memory performance gap

Indexed keywords

ALGORITHMS; BANDWIDTH; BUFFER STORAGE; COMPUTER SIMULATION; DATA COMPRESSION; PARALLEL PROCESSING SYSTEMS; PERFORMANCE; SIMULATORS;

CACHE AND MEMORY COMPRESSION; I/O BOTTLENECK; MEMORY HIERARCHY; PERFORMANCE EVALUATION; PROCESSOR-MEMORY PERFORMANCE GAP;

MICROPROCESSOR CHIPS;

EID: 12344257165     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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