DMP: Deterministic shared memory multiprocessing

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2009, Pages 85-96

  Devietti, Joseph ^a   Lucia, Brandon ^a   Ceze, Luis ^a   Oskin, Mark ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

Design; Performance; Reliability

Indexed keywords

DESIGN; ECONOMIC AND SOCIAL EFFECTS; MEMORY ARCHITECTURE; MULTITASKING; PARALLEL PROGRAMMING; RELIABILITY; SOFTWARE RELIABILITY; SOFTWARE TESTING;

EXISTING SYSTEMS; MULTI PROCESSOR SYSTEMS; MULTI-THREADED APPLICATION; MULTI-THREADED PROGRAMS; MULTITHREADED SOFTWARES; PARALLEL PROGRAM; PERFORMANCE; PERFORMANCE COSTS;

PROGRAM DEBUGGING;

EID: 67650035136     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508244.1508255     Document Type: Conference Paper

References (23)

1. D. Bacon and S. Goldstein. Hardware-Assisted Replay of Multiprocessor Programs. In Workshop on Parallel and Distributed Debugging, 1991.
2. C. Bienia, S. Kumar, J. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In PACT, 2008.
3. S. Gopal, T. N. Vijaykumar, J. E. Smith, and G. S. Sohi. Speculative Versioning Cache. In HPCA, 1998.
4. L. Hammond, M. Willey, and K. Olukotun. Data Speculation Support for a Chip Multiprocessor. In ASPLOS, 1998. (Pubitemid 128488891)
5. L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H.Wijaya, C. Kozyrakis, and K. Olukotun. Transactional Memory Coherence and Consistency. In ISCA, 2004.
6. M. Herlihy and J. E. B. Moss. Transactional Memory: Architectural Support for Lock-Free Data Structures. In ISCA, 1993. (Pubitemid 23675551)
7. D. Hower and M. Hill. Rerun: Exploiting Episodes for Lightweight Memory Race Recording. In ISCA, 2008.
8. J. Choi and H. Srinivasan. Deterministic Replay of Java Multithreaded Applications. In SIGMETRICS SPDT, 1998.
9. V. Krishnan and J. Torrellas. A Chip-Multiprocessor Architecture with Speculative Multithreading. IEEE TC, 1999. (Pubitemid 30524470)
10. C. Lattner and V. Adve. LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. In CGO, 2004.
11. T.J. Leblanc and J.M. Mellor-Crummey. Debugging Parallel Programs with Instant Replay. IEEE TC, April 1987.
12. E. A. Lee. The problem with threads. IEEE Computer, 2006. (Pubitemid 43786509)
13. C. K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. Janapa Reddi, and K. Hazelwood. PIN: Building Customized Program Analysis Tools with Dynamic Instrumentation. In PLDI, 2005. (Pubitemid 43185951)
14. P. Montesinos, L. Ceze, and J. Torrellas. DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently. In ISCA, 2008.
15. S. Narayanasamy, C. Pereira, and B. Calder. Recording Shared Memory Dependencies Using Strata. In ASPLOS, 2006. (Pubitemid 47168403)
16. S. Narayanasamy, G. Pokam, and B. Calder. BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging. In ISCA, 2005. (Pubitemid 41543448)
17. M. Rinard and M. Lam. The design, implementation, and evaluation of Jade. ACM TOPLAS, 1988. (Pubitemid 128446788)
18. M. Ronsee and K. De Bosschere. RecPlay: A Fully Integrated Practical Record/Replay System. ACM TOCS, 1999. (Pubitemid 129541508)
19. G. S. Sohi, S. E. Breach, and T. N. Vijayakumar. Multiscalar Processors. In ISCA, 1995.
20. W. Thies, M. Karczmarek, and S. Amarasinghe. StreamIt: A Language for Streaming Applications. In CC, 2002.
21. S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In ISCA, 1995.
22. M. Xu, R. Bodik, and M. Hill. A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay. In ISCA, 2003.
23. M. Xu, M. Hill, and R. Bodik. A Regulated Transitive Reduction (RTR) for Longer Memory Race Recording. In ASPLOS, 2006. (Pubitemid 47168389)