Collaborative voltage scaling with online STA and variable-latency datapath

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2010, Pages 347-352

  Lin, Tay Jyi ^a,b   Hsiao, Pi Cheng ^a   Lin, Chi Hung ^a   Kuo, Shu Chang ^a   Lin, Chou Kun ^a   Kuo, Yu Ting ^b   Liu, Chih Wei ^b   Chu, Yuan Hua ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

adaptive voltage scaling; collaborative voltage scaling; online STA; variable latency datapath

Indexed keywords

ADAPTIVE VOLTAGE SCALING; CRITICAL PATHS; CYCLE TIME ESTIMATION; DATA PATHS; DEEP SUB-MICRON; DELAY ESTIMATION; EVENT DRIVEN; PROCESS TECHNOLOGIES; RUNTIMES; STATIC TIMING ANALYSIS; SUPPLY VOLTAGES; TEST-CHIP; VOLTAGE-SCALING;

INTEGRATED CIRCUIT TESTING; LAKES;

CRITICAL PATH ANALYSIS;

EID: 77954480374     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1785481.1785560     Document Type: Conference Paper

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