Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2008, Pages 217-220

  Calimera, Andrea ^a   Macii, Enrico ^a   Poncino, Massimo ^a   Bahar, R Iris ^b  

^a POLITECNICO DI TORINO   (Italy)

^b Brown University   (United States)

Author keywords

Logic synthesis; Multi Vt; Temperature aware

Indexed keywords

ATMOSPHERIC TEMPERATURE; CLIMATOLOGY; DESIGN; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; OPTIMIZATION; POWER ELECTRONICS; SYNTHESIS (CHEMICAL); THERMAL EFFECTS; TIME MEASUREMENT; TIMING CIRCUITS;

BOUNDARY TEMPERATURES; CELL SIZES; EFFECTS OF TEMPERATURES; LEAKAGE POWER; LEAKAGE REDUCTIONS; LOGIC SYNTHESIS; MULTI-VT; OPTIMIZATION TECHNIQUES; POWER OPTIMIZATIONS; SUPPLY VOLTAGES; TEMPERATURE EFFECTS; TEMPERATURE INCREASE; TEMPERATURE INVERSIONS; TEMPERATURE-AWARE; TEMPERATURE-AWARE DESIGNS; TIMING ANALYSIS; TIMING ERRORS;

TEMPERATURE;

EID: 57549110028     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1393921.1393978     Document Type: Conference Paper

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