-
1
-
-
46049100422
-
A multilayer stackable thin-film transistor (TFT) NAND-type flash memory
-
Dec.
-
E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, C. P. Lu, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, "A multilayer stackable thin-film transistor (TFT) NAND-type flash memory," in IEDM Tech. Dig., Dec. 2006, pp. 41-44.
-
(2006)
IEDM Tech. Dig.
, pp. 41-44
-
-
Lai, E.K.1
Lue, H.T.2
Hsiao, Y.H.3
Hsieh, J.Y.4
Lu, C.P.5
Wang, S.Y.6
Yang, L.W.7
Yang, T.8
Chen, K.C.9
Gong, J.10
Hsieh, K.Y.11
Liu, R.12
Lu, C.Y.13
-
2
-
-
0034598733
-
Large-scale complementary integrated circuits based on organic transistors
-
Feb.
-
B. Crone, A. Dodabalapur, Y.-Y. Lin, R. W. Filas, Z. Bao, A. LaDuca, R. Sarpeshkar, H. E. Katz, and W. Li, "Large-scale complementary integrated circuits based on organic transistors," Nature, vol.403, no.6769, pp. 521-523, Feb. 2000.
-
(2000)
Nature
, vol.403
, Issue.6769
, pp. 521-523
-
-
Crone, B.1
Dodabalapur, A.2
Lin, Y.-Y.3
Filas, R.W.4
Bao, Z.5
Laduca, A.6
Sarpeshkar, R.7
Katz, H.E.8
Li, W.9
-
3
-
-
0016597193
-
The electrical properties of polycrystalline silicon films
-
Dec.
-
J. Y. W. Seto, "The electrical properties of polycrystalline silicon films," J. Appl. Phys., vol.46, no.12, pp. 5247-5254, Dec. 1975.
-
(1975)
J. Appl. Phys
, vol.46
, Issue.12
, pp. 5247-5254
-
-
Seto, J.Y.W.1
-
4
-
-
0039707974
-
Stochastic model for grain size versus dose in implanted and annealed polycrystalline silicon films on SiO2
-
Jun.
-
R. B. Iverson and R. Reif, "Stochastic model for grain size versus dose in implanted and annealed polycrystalline silicon films on SiO2," J. Appl. Phys., vol.57, no.12, pp. 5169-5175, Jun. 1985.
-
(1985)
J. Appl. Phys
, vol.57
, Issue.12
, pp. 5169-5175
-
-
Iverson, R.B.1
Reif, R.2
-
5
-
-
0030216907
-
Fabrication of high-mobility p-channel poly-Si thin-film transistors by self-aligned metal-induced lateral crystallization
-
Apr.
-
S. W. Lee, T. H. Ihn, and S. K. Joo, "Fabrication of high-mobility p-channel poly-Si thin-film transistors by self-aligned metal-induced lateral crystallization," IEEE Electron Device Lett., vol.17, no.8, pp. 407- 409, Apr. 1996.
-
(1996)
IEEE Electron Device Lett
, vol.17
, Issue.8
, pp. 407-409
-
-
Lee, S.W.1
Ihn, T.H.2
Joo, S.K.3
-
6
-
-
36449004108
-
Phase transformation mechanisms involved in excimer laser crystallization of amorphous silicon films
-
Oct.
-
J. S. Im and H. J. Kim, "Phase transformation mechanisms involved in excimer laser crystallization of amorphous silicon films," Appl. Phys. Lett., vol.63, no.14, pp. 1969-1971, Oct. 1993.
-
(1993)
Appl. Phys. Lett
, vol.63
, Issue.14
, pp. 1969-1971
-
-
Im, J.S.1
Kim, H.J.2
-
7
-
-
0035902938
-
Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species
-
Feb.
-
Y. Cui, Q. Wei, H. Park, and C. M. Lieber, "Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species," Science, vol.293, no.5533, pp. 1289-1292, Feb. 2001.
-
(2001)
Science
, vol.293
, Issue.5533
, pp. 1289-1292
-
-
Cui, Y.1
Wei, Q.2
Park, H.3
Lieber, C.M.4
-
8
-
-
0001405799
-
Nonvolatile memory and programmable logic from molecule-gated nanowires
-
Apr.
-
X. Duan, Y. Huang, and C.M. Lieber, "Nonvolatile memory and programmable logic from molecule-gated nanowires," Nano Lett., vol.2, no.5, pp. 487-490, Apr. 2002.
-
(2002)
Nano Lett
, vol.2
, Issue.5
, pp. 487-490
-
-
Duan, X.1
Huang, Y.2
Lieber, C.M.3
-
9
-
-
29044440093
-
FinFET-A self-aligned double-gate MOSFET scalable to 20 nm
-
Dec.
-
D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, "FinFET-A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol.47, no.12, pp. 2320-2325, Dec. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
Lee, W.C.2
Kedzierski, J.3
Takeuchi, H.4
Asano, K.5
Kuo, C.6
Anderson, E.7
King, T.J.8
Bokor, J.9
Hu, C.10
-
10
-
-
0036932378
-
25-nm CMOS omega FETs
-
Dec.
-
F. L. Yang, H. Y. Chen, F. C. Chen, C. C. Huang, C. Y. Chang, H. K. Chiu, C. C. Lee, C. C. Chen, H. T. Huang, C. J. Chen, H. J. Tao, Y. C. Yeo, M. S. Liang, and C. Hu, "25-nm CMOS omega FETs," in IEDM Tech. Dig., Dec. 2002, pp. 255-258.
-
(2002)
IEDM Tech. Dig.
, pp. 255-258
-
-
Yang, F.L.1
Chen, H.Y.2
Chen, F.C.3
Huang, C.C.4
Chang, C.Y.5
Chiu, H.K.6
Lee, C.C.7
Chen, C.C.8
Huang, H.T.9
Chen, C.J.10
Tao, H.J.11
Yeo, Y.C.12
Liang, M.S.13
Hu, C.14
-
11
-
-
0141761518
-
Trigate fully depleted CMOS transistors: Fabrication, design, and layout
-
Jun.
-
B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, "Trigate fully depleted CMOS transistors: Fabrication, design, and layout," in VLSI Symp. Tech. Dig., Jun. 2003, pp. 133-134.
-
(2003)
VLSI Symp. Tech. Dig.
, pp. 133-134
-
-
Doyle, B.1
Boyanov, B.2
Datta, S.3
Doczy, M.4
Hareland, S.5
Jin, B.6
Kavalieros, J.7
Linton, T.8
Rios, R.9
Chau, R.10
-
12
-
-
62549097281
-
Polycrystalline Si nanowire SONOS nonvolatile memory cell fabricated on a gate-all-around (GAA) channel architecture
-
Mar.
-
J. Fu, Y. Jiang, N. Singh, C. X. Zhu, G. Q. Lo, and D. L. Kwong, "Polycrystalline Si nanowire SONOS nonvolatile memory cell fabricated on a gate-all-around (GAA) channel architecture," IEEE Electron Device Lett., vol.30, no.3, pp. 246-249, Mar. 2009.
-
(2009)
IEEE Electron Device Lett
, vol.30
, Issue.3
, pp. 246-249
-
-
Fu, J.1
Jiang, Y.2
Singh, N.3
Zhu, C.X.4
Lo, G.Q.5
Kwong, D.L.6
-
13
-
-
37549041289
-
Multiple-gate CMOS thin-film transistor with polysilicon nanowire
-
Jan.
-
M. Im, J. W. Han, H. Lee, L. E. Yu, S. Kim, C. H. Kim, S. C. Jeon, K. H. Kim, G. S. Lee, J. S. Oh, Y. C. Park, H. M. Lee, and Y. K. Choi, "Multiple-gate CMOS thin-film transistor with polysilicon nanowire," IEEE Electron Device Lett., vol.29, no.1, pp. 102-105, Jan. 2008.
-
(2008)
IEEE Electron Device Lett
, vol.29
, Issue.1
, pp. 102-105
-
-
Im, M.1
Han, J.W.2
Lee, H.3
Yu, L.E.4
Kim, S.5
Kim, C.H.6
Jeon, S.C.7
Kim, K.H.8
Lee, G.S.9
Oh, J.S.10
Park, Y.C.11
Lee, H.M.12
Choi, Y.K.13
-
14
-
-
71049156288
-
Characteristics of sub-5-nm trigate nanowire MOSFETs with single- and poly-Si channels in SOI structure
-
Jun.
-
S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Yeo, J. K. Ha, H. Lim, H. W. Park, D. W. Kim, T. Y. Chung, K. S. Oh, and W. S. Lee, "Characteristics of sub-5-nm trigate nanowire MOSFETs with single- and poly-Si channels in SOI structure," in VLSI Symp. Tech. Dig., Jun. 2009, pp. 142-143.
-
(2009)
VLSI Symp. Tech. Dig.
, pp. 142-143
-
-
Suk, S.D.1
Li, M.2
Yeoh, Y.Y.3
Yeo, K.H.4
Ha, J.K.5
Lim, H.6
Park, H.W.7
Kim, D.W.8
Chung, T.Y.9
Oh, K.S.10
Lee, W.S.11
-
15
-
-
26444483307
-
A simple and low-cost method to fabrication TFTs with poly-Si nanowire channel
-
Sep.
-
H. C. Lin, M. H. Lee, C. J. Su, T. Y. Huang, C. C. Lee, and Y. S. Yang, "A simple and low-cost method to fabrication TFTs with poly-Si nanowire channel," IEEE Electron Device Lett., vol.26, no.9, pp. 643-645, Sep. 2005.
-
(2005)
IEEE Electron Device Lett
, vol.26
, Issue.9
, pp. 643-645
-
-
Lin, H.C.1
Lee, M.H.2
Su, C.J.3
Huang, T.Y.4
Lee, C.C.5
Yang, Y.S.6
-
16
-
-
47249092862
-
A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate
-
Jul.
-
H. C. Lin, H. H. Hsu, C. J. Su, and T. Y. Huang, "A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate," IEEE Electron Device Lett., vol.29, no.7, pp. 718-720, Jul. 2008.
-
(2008)
IEEE Electron Device Lett
, vol.29
, Issue.7
, pp. 718-720
-
-
Lin, H.C.1
Hsu, H.H.2
Su, C.J.3
Huang, T.Y.4
-
17
-
-
33947202315
-
High-performance poly-Si nanowire NMOS transistors
-
Mar.
-
H. C. Lin and C. J. Su, "High-performance poly-Si nanowire NMOS transistors," IEEE Trans. Nanotechnol., vol.6, no.2, pp. 206-212, Mar. 2007.
-
(2007)
IEEE Trans. Nanotechnol
, vol.6
, Issue.2
, pp. 206-212
-
-
Lin, H.C.1
Su, C.J.2
-
18
-
-
67649382027
-
Performance enhancement in double-gated poly-Si nanowire transistors with reduced nanowire channel thickness
-
Jun.
-
H. C. Lin,W. C. Chen, C. D. Lin, and T. Y. Huang, "Performance enhancement in double-gated poly-Si nanowire transistors with reduced nanowire channel thickness," IEEE Electron Device Lett., vol.30, no.6, pp. 644- 646, Jun. 2009.
-
(2009)
IEEE Electron Device Lett
, vol.30
, Issue.6
, pp. 644-646
-
-
Linw. C Chen, H.C.1
Lin, C.D.2
Huang, T.Y.3
-
19
-
-
33947244195
-
Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels
-
Oct.
-
H. C. Lin, M. H. Lee, C. J. Su, and S. H. Chen, "Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels," IEEE Trans. Electron Devices, vol.53, no.10, pp. 2471-2477, Oct. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.10
, pp. 2471-2477
-
-
Lin, H.C.1
Lee, M.H.2
Su, C.J.3
Chen, S.H.4
-
20
-
-
0003576507
-
-
Englewood Cliffs, NJ: Prentice- Hall
-
J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI Technology: Fundamentals, Practice, and Modeling. Englewood Cliffs, NJ: Prentice- Hall, 2000.
-
(2000)
Silicon VLSI Technology: Fundamentals, Practice, and Modeling
-
-
Plummer, J.D.1
Deal, M.D.2
Griffin, P.B.3
-
21
-
-
77950300559
-
Origins of performance enhancement in independent double-gated poly-Si nanowire devices
-
Apr.
-
H. H. Hsu, H. C. Lin, and T. Y. Huang, "Origins of performance enhancement in independent double-gated poly-Si nanowire devices," IEEE Trans. Electron Devices, vol.57, no.4, pp. 905-912, Apr. 2010.
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, Issue.4
, pp. 905-912
-
-
Hsu, H.H.1
Lin, H.C.2
Huang, T.Y.3
-
22
-
-
0019060104
-
A new method to determine MOSFET channel length
-
Sep.
-
J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho, "A new method to determine MOSFET channel length," IEEE Electron Device Lett., vol.EDL-1, no.9, pp. 170-173, Sep. 1980.
-
(1980)
IEEE Electron Device Lett
, vol.EDL-1
, Issue.9
, pp. 170-173
-
-
Chern, J.G.J.1
Chang, P.2
Motta, R.F.3
Godinho, N.4
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