Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 142-143

  Sung, Dae Suk ^a   Li, Ming ^a   Yun, Young Yeoh ^a   Kyoung, Hwan Yeo ^a   Jae, Kyu Ha ^a   Lim, Hyunseok ^a   Park, HyunWoo ^a   Kim, Dong Won ^a   Chung, TaeYoung ^a   Kyung, Seok Oh ^a   Lee, Won Seong ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BALLISTIC EFFICIENCY; CONVENTIONAL TECHNOLOGY; MOS-FET; NANOWIRE MOSFETS; OFF-LEAKAGE CURRENT; ON STATE CURRENT; POLY-SI; SOI STRUCTURE; TRIGATE;

BIPOLAR TRANSISTORS; FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; MOSFET DEVICES; NANOWIRES; SILICON;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 71049156288     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S.D.Suk et al., IEDM Tech.., p.891, 2007.
2. S.D.Suk et al., VLSI Symp. Tech., p.38, 2008.
3. S.M.Jung et al., VLSI Symp. Tech., p. 228, 2004.
4. M.J.M.Pelgrom et al., IEDM Tech., p. 915, 1998.
5. R.Wang et al., TED, Vol. 55, p. 11, 2008.